# :STATus:LTESt:EVENt?

Operation Status Registers Commands

- :STATus:ADERegister:EVENt?
- :STATus:ADERegister:ENABle
- :STATus:CALibration:EVENt?
- :STATus:CALibration:ENABle
- :STATus:CLIPped:ALL:CONNection:BANK:EVENt?
- :STATus:CLIPped:ALL:CONNection:BANK:ENABle
- :STATus:CLIPped:ALL:CONNection:EVENt?
- :STATus:CLIPped:ALL:CONNection:ENABle
- :STATus:CLIPped:ALL:EVENt?
- :STATus:CLIPped:ALL:ENABle
- :STATus:CLIPped:EVENt?
- :STATus:CLIPped:ENABle
- :STATus:LTESt:EVENt?
- :STATus:LTESt:ENABle
- :STATus:OPERation:EVENt?
- :STATus:OPERation:ENABle
- :STATus:OVERload:ALL:CONNection:BANK:EVENt?
- :STATus:OVERload:ALL:CONNection:BANK:ENABle
- :STATus:OVERload:ALL:CONNection:EVENt?
- :STATus:OVERload:ALL:CONNection:ENABle
- :STATus:OVERload:ALL:EVENt?
- :STATus:OVERload:ALL:ENABle
- :STATus:OVERload:EVENt?
- :STATus:OVERload:ENABle
- :STATus:TRIGger:EVENt?
- :STATus:TRIGger:ENABle

## Query Syntax

    :STATus:LTESt:EVENt?

## Description

Reads the limit test event register to determine the status of individual status bits. The decimal-weighted value of the register is returned. The only bit used is bit 0 (LTEST), which indicated if a limit test has completed.

Reporting of event register bits in the status register system is controlled by the mask loaded into the enable register. All true event bits, that are enabled, are logically "OR"ed, which results in setting true bit 8 (LTEST) of the Operation Status Register.

Use the `:LTESt Subsystem` subsystem to configure a limit test. The limit test event register is used only when a measurement limit test completes.

Limit Test Register Commands
Register | Read | Write | Command
--- | --- | --- | ---
Event | ♦ |  | :STATus:LTESt:EVENt?
Enable (mask) | ♦ | ♦ | :STATus:LTESt:ENABle

Limit Test Status Register Bits
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Bit Weight | 32768 | 16384 | 8192 | 4096 | 2048 | 1024 | 512 | 256 | 128 | 64 | 32 | 16 | 8 | 4 | 2 | 1
Event Register | — | — | — | — | — | — | — | — | — | — | — | — | LLINE | MTEST | ACQ | MEAS
Enable Register |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
Sets | to Bit 9 (LTEST) of Operation Status Register

## Bit Definitions

LLINE
  A true indicates that a limit-line test has completed. Use the `:LLINe Subsystem` to configure a limit-line-based limit test.
MTEST
  A true indicates that the mask test limit test has completed. Use the `:LTESt:MTESt:MRESult{N}:STATe` command to configure a mask limit test.
ACQ
  A true indicates that the specified number of waveforms, samples, or patterns has occurred (acquisition limit test has completed). Use the `:LTESt:ACQuire:STATe` command to configure an acquisition limit test.
MEAS
  A true indicates that the measurements limit test has completed. Use the `:LTESt:MEASure:MLIMit:STATe` command to configure a measurements limit test.