# DDR5

Subtopics

- Equalization (DFE) for DDR5 Signals
- Specifying Thresholds for DDR5 Real-Time Eye
- Setting Acquisition Options for DDR5 Real-Time Eye

The DDR5 clock recovery mode performs clock recovery with read or write discrimination, letting you create a real-time eye of the DQ (Data) waveform. Read or write bursts are separated by analyzing the DQ (Data), DQS (Strobe), and CA4 (Command/Address 4) signals.

DDR5 real-time eye can be performed on signals that have had equalization (DFE) applied or on signals without equalization.

When the DDR5 clock recovery mode is selected, the Clock Recovery Setup dialog box has these controls:

(The DQ source is the waveform of the selected tab, or when the DDR5 clock recovery mode is selected in Global Settings, all channels that Track Global Clock Recovery Settings.)

When using the DDR5 signal type, the specified DQS (Strobe) and CA4 (Command/Address 4) signals are automatically set up as explicit clock signals used for clock recovery.

- Symbol Rate — Enter the signal's expected baud rate.

  The Select From List drop-down menu lets you select typical rates for standard communication interface technologies. The Auto Set Symbol Rate button runs a data rate measurement and populates the Symbol Rate field with the data rate measured on the input signal.

- DQS Source — Select an analog channel, math function, or waveform memory.

- CA4 Source — Select an analog channel, math function, or waveform memory.

- Find Clocks On — Select whether to recover clocks on Read bursts or Write bursts.

- Preamble Length — Specify the preamble length used in the device under test (DUT) for the selected burst type in Find Clocks On.

- Postamble Length — Specify the postamble length used in the device under test (DUT) for the selected burst type in Find Clocks On.

- CA4 Latency — This is the time from the CS4 (Command/Address 4) steady state (high for read bursts, low for write bursts) to the first DQ (Data) edge.

- DQS to DQ Delay — This is the expected or measured tDQS2DQ time for the device under test (DUT). The proper value will align the strobe (clock) with the data bit. Delay/skew can be expected with unmatched paths.

## See Also

- Equalization (DFE) for DDR5 Signals
- Specifying Thresholds for DDR5 Real-Time Eye
- Setting Acquisition Options for DDR5 Real-Time Eye