# :STATus:TERegister:EVENt?

Status Byte Registers Commands

- :STATus:LOCal:EVENt?
- :STATus:LOCal:ENABle
- :STATus:MESSage:EVENt?
- :STATus:MESSage:ENABle
- :STATus:TERegister:EVENt?
- :STATus:TERegister:ENABle
- :STATus:USER:EVENt?
- :STATus:USER:ENABle

## Query Syntax

    :STATus:TERegister:EVENt?

## Description

Reads the Trigger Event Register to determine the status of individual status bits. The decimal-weighted value of the register is returned. The only bit used is bit 0 (TRG), which indicates a hardware trigger has occurred.

Reporting of event register bits in the status register system is controlled by the mask loaded into the enable register. All true event bits, that are enabled, are logically "OR"ed, which results in setting true bit 0 (TRG) of the Status Byte Register.

The TRG event register stays set until it is cleared by reading the register or using the *CLS (clear status) command. If your application needs to detect multiple triggers, clear the trigger event register after each trigger. If you are using the Service Request to interrupt a computer operation when the trigger bit is set, you must clear the event register after each time it is set.

Trigger Event Register Commands
Register | Read | Write | Command
--- | --- | --- | ---
Event | ♦ |  | :STATus:TERegister:EVENt?
Enable (mask) | ♦ | ♦ | :STATus:TERegister:ENABle

Trigger Event Register Bits
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Bit Weight | 32768 | 16384 | 8192 | 4096 | 2048 | 1024 | 512 | 256 | 128 | 64 | 32 | 16 | 8 | 4 | 2 | 1
Event Register | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | TRG
Enable Register |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
Sets | to Bit 0 (TRG) of Status Byte Register

## Bit Definitions

COMP
  A true indicates that a hardware trigger has occurred.