# Equalization (DFE) for DDR5 Signals

When using equalization for DDR5 signals, because you want all unit intervals of DDR5 read or write bursts to appear in the real-time eye, you must enable Seed DFE Taps and specify the appropriate Seed Value that that initial symbols are seeded with. The seed value for DDR5 is a logic 1. The seed value for LPDDR5 is a logic 0. The number of DFE taps (UIs) used for DDR5 is four.

(Normally, DFE excludes the first several symbols from the real-time eye because they are used to seed the DFE. For example, with a four-tap DFE, the first four UIs are not normally included in the real-time eye.)

Also, because read-write separation is used to generate the DDR5 real-time eye, there are bursts of DQS (Strobe) clocks associated with the bursts of read or write data, and then there are intervals with no clocks between bursts. DFE taps need to be reseeded after intervals with no clocks, so you should use the Clock Idle Reseed Time field to specify the minimum time between clocks after which the DFE will be reseeded. This value should be slightly less than the smallest time between the end of one burst and the beginning of the next.

These options appear in the Advanced tab of the Decision Feedback Equalizer Setup dialog box. See DFE Advanced Tab.

For more information on using equalization (DFE) in general, see DFE (Decision Feedback Equalizer) Operator.