# *ESR? (Event Status Register)

Common Commands

- *CLS (Clear Status)
- *ESE (Event Status Enable)
- *ESR? (Event Status Register)
- *IDN? (Identification Number)
- *OPC (Operation Complete)
- *OPT? (Option)
- *RST (Reset)
- *SRE (Service Request Enable)
- *STB? (Status Byte)
- *TRG (Trigger)
- *TST? (Hardware Self Tests)
- *WAI (Wait-to-Continue)

## Query Syntax

    *ESR?

## Description

Reads the Standard Status Event Register to determine the status of individual status bits. The decimal-weighted value of the register is returned.

Reporting of Standard Status Event Register bits in the status register system is controlled by the mask loaded into the enable register. All true event bits, that are enabled, are logically "OR"ed, which results in a Bit 5 (ESB) being set in the Status Byte Register.

To enter a mask into the enable register, use the *ESE common command.

Standard Event Status Register Commands
Register | Read | Write | Command
--- | --- | --- | ---
Event | ♦ |  | *ESR?
Enable (mask) | ♦ | ♦ | *ESE

Standard Status Registers
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Bit Weight | 128 | 64 | 32 | 16 | 8 | 4 | 2 | 1
Event Register | PON | URQ | CME | EXE | DDE | QYE | RQL | OPC
Enable Register |  |  |  |  |  |  |  |
Sets | to Bit 5 (ESB) in Status Byte Register

## Bit Definitions

OPC
  A true indicates that an operation is complete.
RQL
  Not used. Permanently set to zero.
QYE
  A true indicates that a query error has been detected.
DDE
  A true indicates that a device-dependent error has been detected.
EXE
  A true indicates that an an execution error has been detected.
CME
  A true indicates that a command error has been detected.
URQ
  Not used. Permanently set to zero.
PON
  A true indicates that an off-to-on transition has occurred.