# :STATus:OVERload:ALL:CONNection:EVENt?

Operation Status Registers Commands

- :STATus:ADERegister:EVENt?
- :STATus:ADERegister:ENABle
- :STATus:CALibration:EVENt?
- :STATus:CALibration:ENABle
- :STATus:CLIPped:ALL:CONNection:BANK:EVENt?
- :STATus:CLIPped:ALL:CONNection:BANK:ENABle
- :STATus:CLIPped:ALL:CONNection:EVENt?
- :STATus:CLIPped:ALL:CONNection:ENABle
- :STATus:CLIPped:ALL:EVENt?
- :STATus:CLIPped:ALL:ENABle
- :STATus:CLIPped:EVENt?
- :STATus:CLIPped:ENABle
- :STATus:LTESt:EVENt?
- :STATus:LTESt:ENABle
- :STATus:OPERation:EVENt?
- :STATus:OPERation:ENABle
- :STATus:OVERload:ALL:CONNection:BANK:EVENt?
- :STATus:OVERload:ALL:CONNection:BANK:ENABle
- :STATus:OVERload:ALL:CONNection:EVENt?
- :STATus:OVERload:ALL:CONNection:ENABle
- :STATus:OVERload:ALL:EVENt?
- :STATus:OVERload:ALL:ENABle
- :STATus:OVERload:EVENt?
- :STATus:OVERload:ENABle
- :STATus:TRIGger:EVENt?
- :STATus:TRIGger:ENABle

## Query Syntax

    :STATus:OVERload:ALL:CONNectionN:EVENt?

## Description

Reads the Overload All Connection register to see which banks of channels have reported overloads since the last time the register was read.

Reading the register once will clear the status for all instruments.

Reporting of event register bits in the status register system is controlled by the mask loaded into the enable register. All true event bits, that are enabled, are logically "OR"ed, which results in setting true bit N-1 (CONNN) of the Overload All Register.

Overload All Register Commands
Register | Read | Write | Command
--- | --- | --- | ---
Event | ♦ |  | :STATus:OVERload:ALL:CONNection:EVENt?
Enable (mask) | ♦ | ♦ | :STATus:OVERload:ALL:CONNection:ENABle

Overload All Register Bits
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Bit Weight | 32768 | 16384 | 8192 | 4096 | 2048 | 1024 | 512 | 256 | 128 | 64 | 32 | 16 | 8 | 4 | 2 | 1
Event Register | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | BANK1
Enable Register |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
Sets | to Bit N-1 (CONNN) of Overload All Register

## Bit Definitions

BANK1
  A true indicates one or more channels on bank 1 reported an overload since the last time the register was read.