Status Bit Definitions of the Questionable Bandwidth Limit Status Condition Register
|
Bit Position |
Name |
Description |
|
0 |
Channel 15, 16 Bandwidth test summary (questionable bandwidth limit extra status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit extra status event register is set to "1." |
|
1 |
Channel 1 Bandwidth Test Fail (questionable bandwidth limit channel 1 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 1 status event register is set to "1." |
|
2 |
Channel 2 Bandwidth Test Fail (questionable bandwidth limit channel 2 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 2 status event register is set to "1." |
|
3 |
Channel 3 Bandwidth Test Fail (questionable bandwidth limit channel 3 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 3 status event register is set to "1." |
|
4 |
Channel 4 Bandwidth Test Fail (questionable bandwidth limit channel 4 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 4 status event register is set to "1." |
|
5 |
Channel 5 Bandwidth Test Fail (questionable bandwidth limit channel 5 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 5 status event register is set to "1." |
|
6 |
Channel 6 Bandwidth Test Fail (questionable bandwidth limit channel 6 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 6 status event register is set to "1." |
|
7 |
Channel 7 Bandwidth Test Fail (questionable bandwidth limit channel 7 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 7 status event register is set to "1." |
|
8 |
Channel 8 Bandwidth Test Fail (questionable bandwidth limit channel 8 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 8 status event register is set to "1." |
|
9 |
Channel 9 Bandwidth Test Fail (questionable bandwidth limit channel 9 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 9 status event register is set to "1." |
|
10 |
Channel 10 Bandwidth Test Fail (questionable bandwidth limit channel 10 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 10 status event register is set to "1." |
|
11 |
Channel 11 Bandwidth Test Fail (questionable bandwidth limit channel 11 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 11 status event register is set to "1." |
|
12 |
Channel 12 Bandwidth Test Fail (questionable bandwidth limit channel 12 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 12 status event register is set to "1." |
|
13 |
Channel 13 Bandwidth Test Fail (questionable bandwidth limit channel 13 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 13 status event register is set to "1." |
|
14 |
Channel 14 Bandwidth Test Fail (questionable bandwidth limit channel 14 status register summary) |
Set to "1" while one of the enabled bits in the questionable bandwidth limit channel 14 status event register is set to "1." |
|
15 |
Not used |
Always 0 |
Issuing the *CLS command will clear all bits from the questionable bandwidth limit status event register.