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Programming the Instrument

This section provides information about the instrument's SCPI programming interface.

IEEE Command Descriptions

STATus Subsystem Overview

What Are Status Registers

What Are Status Register SCPI Commands

How to Use the Status Registers

Status Register Bit Parameters

STATus Subsystem Registers and Commands

Status Register Diagrams

Status Byte Register

Standard Event Status Register

STATus:OPERation Register

STATus:OPERation:ALIGning Register

STATus:OPERation:ALIGning:EALigning Register

STATus:OPERation:SETTling Register

STATus:OPERation:SETTling:ESETtling Register

STATus:OPERation:WFTRigger Register

STATus:OPERation:WFTRigger:EWFTrigger Register

STATus:OPERation:WFTRigger:WFTGroup Registers

STATus:QUEStionable Register

STATus:QUEStionable:OVERload Register

STATus:QUEStionable:OVERload:EOVerload Register

STATus:QUEStionable:POWer Register

STATus:QUEStionable:POWer:UNLeveled Register

STATus:QUEStionable:POWer:UNLeveled:EUNLeveled Register

STATus:QUEStionable:POWer:PAMax Register

STATus:QUEStionable:POWer:PAMax:EPAMax Register

STATus:QUEStionable:POWer Register

STATus:QUEStionable:FREQuency Register

STATus:QUEStionable:ANEeded Register

STATus:QUEStionable:ANEeded:EANeeded Register

STATus:QUEStionable:CALibration Register

STATus:QUEStionable:CALibration:AFAiled Register

STATus:QUEStionable:CALibration:AFAiled:EAFailed Register

STATus:QUEStionable:CALibration:IQDFailed Register

STATus:QUEStionable:CALibration:IQDFailed:EIQDfailed Register

STATus:QUEStionable:CALibration:PSFailed Register

STATus:QUEStionable:CALibration:PSFailed:EPSFailed Register

STATus:QUEStionable:CALibration:MCFailed Register

STATus:QUEStionable:CALibration:MCFailed:EMCFailed Register

STATus:QUEStionable:STFailed Register

STATus:QUEStionable:STFailed:ESTFailed Register

IEEE Command Descriptions

The instrument supports the following subset of IEEE 488.2 Common Commands, as defined in Chapter 10 of IEEE Standard 488.2–1992. As indicated below, some of these commands correspond directly to instrument front-panel functionality, while others are available only as remote commands.

• *CAL? - Calibration Query (Internal Alignments equivalent)

• *CLS - Clear Status

• *ESE - Standard Event Status Enable

• *ESR? - Standard Event Status Register Query

• *IDN? - Identification Query

• *OPC? - Operation Complete

• *OPT? - Query Instrument Options

• Query Options per Channel

• Set *OPT Response

• *RST - Reset (Mode Preset equivalent)

• *SRE - Service Request Enable

• *STB? - Status Byte Query

• *TRG - Trigger

• *TST? - Self Test Query

• *WAI - Wait-to-Continue

*CAL? - Calibration Query

Performs a full alignment and returns a number indicating the success of the alignment. A zero is returned if the alignment is successful. A one is returned if any part of the alignment fails. *CAL? is the same as doing a CAL:INT? for all channels.

*CLS - Clear Status

Clears the status byte register. It does this by emptying the error queue and clearing all bits in all of the event registers, and consequently all bits in the Status Byte register.

The Status Byte register summarizes the states of the other registers. It is also responsible for generating service requests.

*ESE - Standard Event Status Enable

Sets the desired bits in the Event Enable Register of the Standard Event Status Register, which enables the corresponding bits in the Standard Event Status register. This register monitors I/O errors and synchronization conditions such as operation complete, request control, query error, device dependent error, status execution error, command error, and power on. The selected bits are OR’d to become a summary bit (bit 5) in the byte register which can be queried.

The query returns the state of the standard event status enable register.

Numeric values for bit patterns can be entered using decimal or hexadecimal representations (that is, 0 to 32767 is equivalent to #H0 to #H7FFF).

*ESR? - Standard Event Status Register Query

Queries and clears the Standard Event Status Register. (This is a destructive read.) The value returned is a hexadecimal number that reflects the current state (0/1) of all the bits in the register.

*IDN? - Identification Query

Returns a string of instrument identification information. The string will contain the model number, serial number, and firmware revision.

The response is organized into four fields separated by commas. The field definitions are as follows:

• Manufacturer

• Model

• Serial number

• Firmware version

*OPC? - Operation Complete

Sets bit 0 in the standard event status register (SER) to "1" when pending operations have finished, that is when all overlapped commands are complete. It does not hold off subsequent operations. You can determine when the overlapped commands have completed either by polling the OPC bit in SER, or by setting up the status system such that a service request (SRQ) is asserted when the OPC bit is set.

The *OPC? query returns a "1" after all the current overlapped commands are complete. So it holds off subsequent commands until the "1” is returned, then the program continues. This query can be used to synchronize events of other instruments on the external bus.

*OPT? - Query Instrument Options

Returns a string of all the installed instrument options. It is a comma separated list, such as: 001,002,016,1E1,1EA,1EH,320,A01,D21,F11,F14,F21,F44,M04,M10,PCH,PM1,ST6,UNQ,UNT,UNZ

For the M9383B/M9384B all instrument options are listed in the response.

For theM9484C, *OPT? contains the options for channel 1 and options that pertain to the instrument regardless of how many channels are present. With the M9484C, if there are more than 1 channel present the last entry in the list will be ‘…’ which is a sentinel to indicate :SYSTem:RF<channel>:OPT? is used to query the options for channels 2 through the total number of channels.

Query Options per Channel

For instruments with more than one RF channel, this query is used to retrieve the options that are specific for each channel.

Set *OPT Response

Remote command only

The default response of the *OPT? query are the options that pertain to the M9383B/M9384B in use. This command is provided to enable the *OPT? response to emulate the options of another instrument. This command can be used if you are reusing test software written for another instrument which expects a specific *OPT? response. Caution should be used emulating options of another instrument to ensure the M9383B/M9384B in use meets the RF performance of the testing scenario.

The instrument options displayed on the System Information screen are unaffected by any custom setting of *OPT?; the System Information screen always displays the options of the M9383B/M9384B.

When the instrument is power cycled, or the instrument application is restarted, the custom setting of *OPT? is restored to the options of the M9383B/M9384B. Invoking a Restore System Settings to Default Values also restores the *OPT? response to the options of the M9383B/M9384B.

*RST - Reset

Equivalent to :SYST:PRES, which is a basic Preset function. It restores all variables to a Preset state except for Persistent variables. It Includes all signals and all RF Outputs.

*RST clears all pending OPC bits.

*SRE - Service Request Enable

Enables the desired bits of the Service Request Enable Register.

The query returns the value of the register, indicating which bits are currently enabled.

Numeric values for bit patterns can be entered using decimal or hexadecimal representations. (that is,. 0 to 32767 is equivalent to #H0 to #H7FFF).

*STB? - Status Byte Query

Returns the value of the Status Byte Register without erasing its contents.

*TRG - Trigger

Triggers the instrument.

*TST? - Self Test Query

This query performs the internal self-test routines for all RF channels and returns a number indicating the overall success of the testing. A zero is returned if the test is successful, 1 if it fails.

*WAI - Wait-to-Continue

Causes the instrument to wait until all overlapped commands are completed before executing any additional commands. There is no query form for the command.

STATus Subsystem Overview

The SCPI STATus Subsystem allows you to monitor a number of status conditions within the instrument through the use of a hierarchy of status registers containing bits which go true or false depending on various conditions.

This section provides an overview of SCPI status registers and how to manage them. Section STATus Subsystem Registers and Commands provides detailed programming information for each of the status registers.

What Are Status Registers

The status system contains multiple registers that are arranged in a hierarchical order. The lower-level status registers propagate their data to the higher-level registers in the data structures by means of summary bits. The status byte register is at the top of the hierarchy and contains general status information for the instrument’s events and conditions. All other individual registers are used to determine the specific events or conditions. For a diagram of the registers and their interconnections, see above.

The operation and questionable status registers are sets of registers that monitor the overall instrument condition. They are accessed with the STATus:OPERation and STATus:QUEStionable commands in the STATus command subsystem. Each register set is made up of five registers:

• Condition Register—Reports the real-time state of the signals monitored by this register set. There is no latching or buffering for a condition register.

• Positive Transition Register—Controls which signals will set a bit in the event register when the signal makes a low to high transition (when the condition bit changes from 0 to 1).

• Negative Transition Register—Controls which signals will set a bit in the event register when the signal makes a high to low transition (when the condition bit changes from 1 to 0).

• Event Register—Latches any signal state changes, in the way specified by the filter registers. Bits in the event register are never cleared by signal state changes. Event registers are cleared when read. They are also cleared by *CLS and by presetting the instrument.

• Event Enable Register—Controls which of the bits, being set in the event register and will be summarized as a single output for the register set. Summary bits are then used by the next higher register.

The STATus:QUEStionable registers report abnormal operating conditions. The status register hierarchy is:

1. The summary outputs from the six STATus:QUEStionable:<keyword> detail registers are inputs to the STATus:QUEStionable register.

2. The summary output from the STATus:QUEStionable register is an input to the Status Byte Register. See the overall system in the figure at the beginning of this section.

The STATus:OPERation register set has no summarized inputs. The inputs to the STATus:OPERation:CONDition register indicate the real time state of the instrument. The STATus:OPERation:EVENt register summary output is an input to the Status Byte Register.

What Are Status Register SCPI Commands

Monitoring of the instrument conditions is done at the highest level using the following IEEE 488.2 common commands. Complete command descriptions are available in section IEEE Command Descriptions. Individual status registers can be set and queried using the commands in the STATus Subsystem Registers and Commands section.

• *CLS (clear status) clears the status byte by emptying the error queue and clearing all the event registers.

• *ESE, *ESE? (event status enable) sets and queries the bits in the enable register part of the standard event status register.

• *ESR? (event status register) queries and clears the event register part of the standard event status register.

• *OPC, *OPC? (operation complete) sets the standard event status register to monitor the completion of all commands. The query stops any new commands from being processed until the current processing is complete, then returns a ‘1’.

• *PSC, *PSC? (power-on state clear) sets the power-on state so that it clears the service request enable register and the event status enable register at power on.

• *SRE, *SRE? (service request enable) sets and queries the value of the service request enable register.

• *STB? (status byte) queries the value of the status byte register without erasing its contents.

How to Use the Status Registers

A program often needs to be able to detect and manage error conditions or changes in instrument status. There are two methods you can use to programmatically access the information in status registers:

• The polling method

• The service request (SRQ) method

In the polling method, the instrument has a passive role. It only tells the controller that conditions have changed when the controller asks the right question. In the SRQ method, the instrument takes a more active role. It tells the controller when there has been a condition change without the controller asking. Either method allows you to monitor one or more conditions.

The polling method works well if you do not need to know about changes the moment they occur. The SRQ method should be used if you must know immediately when a condition changes. To detect a change using the polling method, the program must repeatedly read the registers.

Use the SRQ method when:

• you need time-critical notification of changes

• you are monitoring more than one device which supports SRQs

• you need to have the controller do something else while waiting

• you cannot afford the performance penalty inherent to polling

Use polling when:

• your programming language/development environment does not support SRQ interrupts

• you want to write a simple, single-purpose program and do not want the added complexity of setting up an SRQ handler

• To monitor a condition:

  • Determine which register contains the bit that reports the condition.

  • Send the unique SCPI query that reads that register.

  • Examine the bit to see if the condition has changed.

You can monitor conditions in different ways.

• Check the current instrument hardware and firmware status. Do this by querying the condition registers which continuously monitor status. These registers represent the current state of the instrument. Bits in a condition register are updated in real time. When the condition monitored by a particular bit becomes true, the bit is set to 1. When the condition becomes false, the bit is reset to 0.

• Monitor a particular condition (bit). You can enable a particular bit(s), using the event enable register. The instrument will then monitor that particular condition(s). If the bit becomes true (0 to 1 transition) in the event register, it will stay set until the event register is cleared. Querying the event register allows you to detect that this condition occurred even if the condition no longer exists. The event register can only be cleared by querying it or sending the *CLS command.

• Monitor a particular type of change in a condition (bit).

  • The transition registers are preset to register if the condition goes from 0 to 1 (false to true, or a positive transition).

  • This can be changed so the selected condition is detected if the bit goes from 1 to 0 (true to false, or a negative transition).

  • It can also be set for both types of transitions occurring.

  • Or it can be set for neither transition. If both transition registers are set to 0 for a particular bit position, that bit will not be set in the event register for either type of change.

Using the Service Request (SRQ) Method

Your language, bus, and programming environment must be able to support SRQ interrupts. (For example, BASIC used with VXI-11.3 (GPIB over LAN). When you monitor a condition with the SRQ method, you must:

1. Determine which bit monitors the condition.

2. Determine how that bit reports to the request service (RQS) bit of the status byte.

3. Send SCPI commands to enable the bit that monitors the condition and to enable the summary bits that report the condition to the RQS bit.

4. Enable the controller to respond to service requests.

When the condition changes, the instrument sets its RQS bit. The controller is informed of the change as soon as it occurs. As a result, the time the controller would otherwise have used to monitor the condition can be used to perform other tasks. Your program determines how the controller responds to the SRQ.

Bit 6 of the status byte register is the request service (RQS) bit. The *SRE command is used to configure the RQS bit to report changes in instrument status. When such a change occurs, the RQS bit is set. It is cleared when the status byte register is queried using *SRE? (with a serial poll.) It can be queried without erasing the contents with *STB?.

When a register being set causes a summary bit in the status byte to change from 0 to 1, the instrument can initiate the service request (SRQ) process. However, the process is only initiated if both of the following conditions are true:

• The corresponding bit of the service request enable register is also set to 1.

• The instrument does not have a service request pending. (A service request is considered to be pending between the time the instrument’s SRQ process is initiated and the time the controller reads the status byte register.)

The SRQ process sets the SRQ true. It also sets the status byte’s request service (RQS) bit to 1. Both actions are necessary to inform the controller that the instrument requires service. Setting the SRQ line only informs the controller that some device on the bus requires service. Setting the RQS bit allows the controller to determine which instrument requires service.

If your program enables the controller to detect and respond to service requests, it should instruct the controller to perform a serial poll when the SRQ is set true. Each device on the bus returns the contents of its status byte register in response to this poll. The device who's RQS bit is set to 1 is the device that requested service.

Status Register Bit Parameters

The figure below shows a typical status register, the Standard Operation Event Enable register. Each bit in a register is represented by a numerical value based on its location. This number is sent with the command to enable a particular bit. If you want to enable more than one bit, you would send the sum of all the bits that you want to monitor.

Figure: Status Register Bit Values

Example 1:

1. To enable bit 0 and bit 6 of standard event status register, you would send the command *ESE 65 because 1 + 64 = 65.

2. The results of a query are evaluated in a similar way. If the *STB? command returns a decimal value of 140, (140 = 128 + 8 + 4) then bit 7 is true, bit 3 is true and bit 2 is true.

Example 2:

1. Suppose you want to know if an Auto-trigger Timeout occurs, but you only cared about that specific condition. So you would want to know what was happening with bit 10 in the Status Questionable Integrity register, and not about any other bits.

2. It is usually a good idea to start by clearing all the status registers with *CLS.

3. Sending the STAT:QUES:INT:ENAB 1024 command lets you monitor only bit 10 events, instead of the default monitoring all the bits in the register. The register default is for positive transition events (0 to 1 transition). That is, when an auto-trigger timeout occurs. If instead, you wanted to know when the Auto-trigger timeout condition is cleared, then you would set the STAT:QUES:INT:PTR 0 and the STAT:QUES:INT:NTR 32767.

4. So now the only output from the Status Questionable Integrity register will come from a bit 10 positive transition. That output goes to the Integrity Sum bit 9 of the Status Questionable register.

5. You can do a similar action with this register to only look at bit 9 using, STAT:QUES:ENAB 512.

6. The Status Questionable register output goes to the “Status Questionable Summary” bit 3 of the Status Byte Register. The output from this register can be enabled using the *SRE 8 command.

7. Finally, you would use the serial polling functionality available for the particular bus/software that you are using to monitor the Status Byte Register. (You could also use *STB? to poll the Status Byte Register.)

STATus Subsystem Registers and Commands

The STATus subsystem remote commands set and query the status registers. This system of registers monitor various events and conditions in the instrument. Software written to control the instrument may need to monitor some of these events and conditions.

Specific status bits are assigned to monitor various aspects of the instrument operation and status. See the Status Register Diagrams for information about the bit assignments and status register interconnections. See also the Instrument Messages for more detail on the instrument conditions that can cause these bits to be set.

The STATus subsystem controls and queries the SCPI-defined instrument status reporting structures. Each status register has a set of five commands used for querying or masking that particular register.

Numeric values for bit patterns can be entered using decimal or hexadecimal representations. (i.e. 0 to 32767 is equivalent to #H0 to #H7FFF. It is also equal to all ones, 111111111111111). See Status Register Bit Parameters for information about using bit patterns for variable parameters.

Status Register Diagrams

The following diagrams provide a graphical overview of the Status Register subsystem.

Status Register Diagram 1 of 2 (View larger image)

Status Register Diagram 2 of 2 (View larger image)

Status Byte Register

Provides a one-byte overview of the entire STATus subsystem. All other registers funnel into this register with summary bits, as shown in the Status Register Diagram.

To query the status byte register, send the command *STB? The response will be the decimal sum of the bits which are set to 1. For example, if bit number 7 and bit number 3 are set to 1, the decimal sum of the 2 bits is 128 plus 8. So the decimal value 136 is returned. The *STB command does not clear the status register.

The RQS bit is read and reset by a serial poll. The same bit position (MSS) is read, non-destructively by the *STB? command. If you serial poll bit 6 it is read as RQS, but if you send *STB it reads bit 6 as MSS. For more information refer to IEEE 488.2 standards, section 11. In addition to the status byte register, the status byte group also contains the service request enable register. This register lets you choose which bits in the status byte register will trigger a service request.

See also *STB? - Status Byte Query.

Service Request Enable Register

Enables the desired bits of the Service Request (SRQ) subsystem.

Send the *SRE <integer> command, where <integer> is the sum of the decimal values of the bits you want to enable plus the decimal value of bit 6. For example, assume that you want to enable bit 7 so that whenever the standard operation status register summary bit is set to 1 it will trigger a service request. Send the command *SRE 192 (because 192 = 128 + 64). You must always add 64 (the numeric value of RQS bit 6) to your numeric sum when you enable any bits for a service request.

The command *SRE? returns the decimal value of the sum of the bits previously enabled with the *SRE <integer> command.

The service request enable register presets to zeros (0).

See also *SRE - Service Request Enable .

Preset the Status Byte

Sets bits in most of the enable and transition registers to their default state. It presets all the Transition Filters, Enable Registers, and the Error/Event Queue Enable. It has no effect on Event Registers, Error/Event QUEue, IEEE 488.2 ESE, and SRE Registers as described in IEEE Standard 488.2-1992, IEEE Standard Codes, Formats, Protocols, and Common Commands for Use with ANSI/IEEE Std 488.1-1987. New York, NY, 1992.

Standard Event Status Register

The standard event status register contains the following bits:

The standard event status register is used to determine the specific event that set bit 5 in the status byte register. To query the standard event status register, send the command *ESR?. The response will be the decimal sum of the bits which are enabled (set to 1). For example, if bit number 7 and bit number 3 are enabled, the decimal sum of the 2 bits is 128 plus 8. So the decimal value 136 is returned. See also the *ESR? - Standard Event Status Register Query .

The Standard Event Status Enable Register

In addition to the standard event status register, the standard event status group also contains a standard event status enable register. This register lets you choose which bits in the standard event status register will set the summary bit (bit 5 of the status byte register) to 1. Send the *ESE <integer> command where <integer> is the sum of the decimal values of the bits you want to enable. For example, to enable bit 7 and bit 6 so that whenever either of those bits is set to 1, the standard event status summary bit of the status byte register will be set to 1, send the command *ESE 192 (128 + 64). The command *ESE? returns the decimal value of the sum of the bits previously enabled with the *ESE <integer> command.

The standard event status enable register presets to zeros (0).

See also *ESE - Standard Event Status Enable .

STATus:OPERation Register

The operation and questionable status registers monitor the overall instrument condition. They are accessed with the STATus:OPERation and STATus:QUEStionable commands.

The operation status register monitors the current instrument state and various instrument operations for a quick summary of what is happening within the instrument. It checks to see if the instrument is calibrating, sweeping, or waiting for a trigger. See also *OPC? - Operation Complete .

Operation Condition Query

Returns the decimal value of the sum of the bits in the Status Operation Condition register.

Operation Condition Query by bit

Returns the value of the indicated bit in the Status Operation Condition register.

Operation Enable

Determines which bits in the Operation Event register, will set the Operation Status Summary bit (bit 7) in the Status Byte Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Operation Enable by bit

Permits setting or querying an individual bit in the Operation Status register.

Operation Event Query

Returns the decimal value of the sum of the bits in the Operation Event register.

Operation Event Query by bit

Returns the indicated bit in the Operation Event register

Operation Negative Transition

Determines which bits in the Operation Condition register will set the corresponding bit in the Operation Event register, when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation Negative Transition by bit

Provides individual bit access to the Operation Condition Negative Transition register.

Operation Positive Transition

Determines which bits in the Operation Condition register will set the corresponding bit in the Operation Event register, when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation Positive Transition by bit

Provides individual bit access to the Operation Condition Positive Transition register.

STATus:OPERation:ALIGning Register

The operation ALIGning register indicates the channels that have raised an alignment in progress condition.

Operation ALIGning Condition

This query returns the decimal value of the sum of the bits in the Operation ALIGning Condition register.

Operation ALIGning Condition by bit

This query returns the value of the indicated bit in the Operation ALIGning Condition register.

Operation ALIGning Enable

This command determines which bits in the Operation ALIGning Event register will set the Aligning Summary bit (bit 0) in the Status Operation Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Operation ALIGning Enable by bit

This command permits setting or querying and individual bit in the Operation ALIGning Enable register

Operation ALIGning Event Query

This query returns the decimal value of the sum of the bits in the Operation ALIGning Event register.

Operation ALIGning Event Query by bit

This query returns the value of the indicated bit in the Operation ALIGning Event register.

Operation ALIGning Negative Transition

This command determines which bits in the Operation ALIGning Condition register will set the corresponding bit in the Operation ALIGning Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation ALIGning Negative Transition by bit

This command provides individual bit access to the Operation ALIGning Condition Negative Transition register.

Operation ALIGning Positive Transition

This command determines which bits in the Operation ALIGning Condition register will set the corresponding bit in the Operation ALIGning Event register when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation ALIGning Positive Transition by bit

This command provides individual bit access to the Operation ALIGning Condition Positive Transition register.

STATus:OPERation:ALIGning:EALigning Register

The operation ALIGning EALigning (Extended Aligning) register indicates if channels 9 through 16 have raised an alignment in progress condition.

Operation ALIGning EALigning Condition

This query returns the decimal value of the sum of the bits in the Operation ALIGning EALigning Condition register.

Operation ALIGning EALigning Condition by bit

This query returns the value of the indicated bit in the Operation ALIGning EALigning Condition register.

Operation ALIGning EALigning Enable

This command determines which bits in the Operation ALIGning EALigning Event register will set the Channels 9 to 16 Summary bit (bit8) in the Status Operation ALIGning Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Operation ALIGning EALigning Enable by bit

This command permits setting or querying and individual bit in the Operation ALIGning EALigning Enable register

Operation ALIGning EALigning Event Query

This query returns the decimal value of the sum of the bits in the Operation ALIGning EALigning Event register.

Operation ALIGning EALigning Event Query by bit

This query returns the value of the indicated bit in the Operation ALIGning EALigning Event register.

Operation ALIGning EALigning Negative Transition

This command determines which bits in the Operation ALIGning EALigning Condition register will set the corresponding bit in the Operation ALIGning EALigning Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation ALIGning EALigning Negative Transition by bit

This command provides individual bit access to the Operation ALIGning EALigning Condition Negative Transition register.

Operation ALIGning EALigning Positive Transition

This command determines which bits in the Operation ALIGning EALigning Condition register will set the corresponding bit in the Operation ALIGning EALigning Event register when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation ALIGning EALigning Positive Transition by bit

This command provides individual bit access to the Operation ALIGning EALigning Condition Positive Transition register.

STATus:OPERation:SETTling Register

The operation SETTling register indicates the channels that have raised a circuitry is settling condition.

Operation SETTling Condition

This query returns the decimal value of the sum of the bits in the Operation SETTling Condition register.

Operation SETTling Condition by bit

This query returns the value of the indicated bit in the Operation SETTling Condition register.

Operation SETTling Enable

This command determines which bits in the Operation SETTling Event register will set the Settling Summary bit (bit1) in the Status Operation Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Operation SETTling Enable by bit

This command permits setting or querying and individual bit in the Operation SETTling Enable register

Operation SETTling Event Query

This query returns the decimal value of the sum of the bits in the Operation SETTling Event register.

Operation SETTling Event Query by bit

This query returns the value of the indicated bit in the Operation SETTling Event register.

Operation SETTling Negative Transition

This command determines which bits in the Operation SETTling Condition register will set the corresponding bit in the Operation SETTling Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation SETTling Negative Transition by bit

This command provides individual bit access to the Operation SETTling Condition Negative Transition register.

Operation SETTling Positive Transition

This command determines which bits in the Operation SETTling Condition register will set the corresponding bit in the Operation SETTling Event register when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation SETTling Positive Transition by bit

This command provides individual bit access to the Operation SETTling Condition Positive Transition register.

STATus:OPERation:SETTling:ESETtling Register

The operation SETTling ESETtling (Extended Settling) register indicates if channels 9 through 16 have raised a circuitry is settling condition.

Operation SETTling ESETtling Condition

This query returns the decimal value of the sum of the bits in the Operation SETTling ESETtling Condition register.

Operation SETTling ESETtling Condition by bit

This query returns the value of the indicated bit in the Operation SETTling ESETtling Condition register.

Operation SETTling ESETtling Enable

This command determines which bits in the Operation SETTling ESETtling Event register will set the Channels 9 to 16 Summary bit (bit8) in the Status Operation SETTling Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Operation SETTling ESETtling Enable by bit

This command permits setting or querying and individual bit in the Operation SETTling ESETtling Enable register

Operation SETTling ESETtling Event Query

This query returns the decimal value of the sum of the bits in the Operation SETTling ESETtling Event register.

Operation SETTling ESETtling Event Query by bit

This query returns the value of the indicated bit in the Operation SETTling ESETtling Event register.

Operation SETTling ESETtling Negative Transition

This command determines which bits in the Operation SETTling ESETtling Condition register will set the corresponding bit in the Operation SETTling ESETtling Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation SETTling ESETtling Negative Transition by bit

This command provides individual bit access to the Operation SETTling ESETtling Condition Negative Transition register.

Operation SETTling ESETtling Positive Transition

This command determines which bits in the Operation SETTling ESETtling Condition register will set the corresponding bit in the Operation SETTling ESETtling Event register when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation SETTling ESETtling Positive Transition by bit

This command provides individual bit access to the Operation SETTling ESETtling Condition Positive Transition register.

STATus:OPERation:WFTRigger Register

The operation WFTRigger register indicates the groups that have raised a waiting for trigger condition.

Operation WFTRigger Condition

This query returns the decimal value of the sum of the bits in the Operation WFTRigger Condition register.

Operation WFTRigger Condition by bit

This query returns the value of the indicated bit in the Operation WFTRigger Condition register.

Operation WFTRigger Enable

This command determines which bits in the Operation WFTRigger Event register will set the Waiting For Trigger Summary bit (bit5) in the Status Operation Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Operation WFTRigger Enable by bit

This command permits setting or querying and individual bit in the Operation WFTRigger Enable register

Operation WFTRigger Event Query

This query returns the decimal value of the sum of the bits in the Operation WFTRigger Event register.

Operation WFTRigger Event Query by bit

This query returns the value of the indicated bit in the Operation WFTRigger Event register.

Operation WFTRigger Negative Transition

This command determines which bits in the Operation WFTRigger Condition register will set the corresponding bit in the Operation WFTRigger Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation WFTRigger Negative Transition by bit

This command provides individual bit access to the Operation WFTRigger Condition Negative Transition register.

Operation WFTRigger Positive Transition

This command determines which bits in the Operation WFTRigger Condition register will set the corresponding bit in the Operation WFTRigger Event register when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation WFTRigger Positive Transition by bit

This command provides individual bit access to the Operation WFTRigger Condition Positive Transition register.

STATus:OPERation:WFTRigger:EWFTrigger Register

The operation WFTRigger EWFTrigger (Extended Waiting For Trigger) register indicates if groups 9 through 16 have raised a waiting for trigger condition.

Operation WFTRigger EWFTrigger Condition

This query returns the decimal value of the sum of the bits in the Operation WFTRigger EWFTrigger Condition register.

Operation WFTRigger EWFTrigger Condition by bit

This query returns the value of the indicated bit in the Operation WFTRigger EWFTrigger Condition register.

Operation WFTRigger EWFTrigger Enable

This command determines which bits in the Operation WFTRigger EWFTrigger Event register will set the Groups 9 to 16 Summary bit (bit8) in the Status Operation WFTRigger Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Operation WFTRigger EWFTrigger Enable by bit

This command permits setting or querying and individual bit in the Operation WFTRigger EWFTrigger Enable register

Operation WFTRigger EWFTrigger Event Query

This query returns the decimal value of the sum of the bits in the Operation WFTRigger EWFTrigger Event register.

Operation WFTRigger EWFTrigger Event Query by bit

This query returns the value of the indicated bit in the Operation WFTRigger EWFTrigger Event register.

Operation WFTRigger EWFTrigger Negative Transition

This command determines which bits in the Operation WFTRigger EWFTrigger Condition register will set the corresponding bit in the Operation WFTRigger EWFTrigger Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation WFTRigger EWFTrigger Negative Transition by bit

This command provides individual bit access to the Operation WFTRigger EWFTrigger Condition Negative Transition register.

Operation WFTRigger EWFTrigger Positive Transition

This command determines which bits in the Operation WFTRigger EWFTrigger Condition register will set the corresponding bit in the Operation WFTRigger EWFTrigger Event register when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation WFTRigger EWFTrigger Positive Transition by bit

This command provides individual bit access to the Operation WFTRigger EWFTrigger Condition Positive Transition register.

STATus:OPERation:WFTRigger:WFTGroup Registers

The operation WFTRigger WFTGroup (Waiting For TRigger Group) register indicates the signal(s) in the group that have raised a waiting for trigger condition.

Operation WFTRigger WFTGroup Condition

This query returns the decimal value of the sum of the bits in the Operation WFTRigger WFTGroup Condition register.

Operation WFTRigger WFTGroup Condition by bit

This query returns the value of the indicated bit in the Operation WFTRigger WFTGroup Condition register.

Operation WFTRigger WFTGroup Enable

This command determines which bits in the Operation WFTRigger WFTGroup, group number, Event register will set the corresponding bit in the Status Operation WFTRigger or WFTRigger EWFTrigger Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Operation WFTRigger WFTGroup Enable by bit

This command permits setting or querying and individual bit in the Operation WFTRigger WFTGroup Enable register

Operation WFTRigger WFTGroup Event Query

This query returns the decimal value of the sum of the bits in the Operation WFTRigger WFTGroup Event register.

Operation WFTRigger WFTGroup Event Query by bit

This query returns the value of the indicated bit in the Operation WFTRigger WFTGroup Event register.

Operation WFTRigger WFTGroup Negative Transition

This command determines which bits in the Operation WFTRigger WFTGroup Condition register will set the corresponding bit in the Operation WFTRigger WFTGroup Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation WFTRigger WFTGroup Negative Transition by bit

This command provides individual bit access to the Operation WFTRigger WFTGroup Condition Negative Transition register.

Operation WFTRigger WFTGroup Positive Transition

This command determines which bits in the Operation WFTRigger WFTGroup Condition register will set the corresponding bit in the Operation WFTRigger WFTGroup Event register when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Operation WFTRigger WFTGroup Positive Transition by bit

This command provides individual bit access to the Operation WFTRigger WFTGroup Condition Positive Transition register.

STATus:QUEStionable Register

The operation and questionable status registers monitor the overall instrument condition. They are accessed with the STATus:OPERation and STATus:QUEStionable commands.

The questionable status register monitors the instrument’s condition to see if anything questionable has happened to it. It is looking for anything that might cause an error or a bad signal like a hardware problem, an out of calibration situation, or an unusual signal. All the bits are summary bits from lower-level event registers.

Questionable Condition

Returns the decimal value of the sum of the bits in the Questionable Condition register.

Questionable Condition by bit

Returns the value of the indicated bit in the Questionable Condition register.

Questionable Enable

Determines which bits in the Questionable Event register will set the Questionable Status Summary bit (bit3) in the Status Byte Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Questionable Enable by bit

Permits setting or querying an individual bit in the Questionable Status register.

Questionable Event Query

Returns the decimal value of the sum of the bits in the Questionable Event register.

Questionable Event Query by bit

Returns the value of the indicated bit in the Questionable Event register.

Questionable Negative Transition

Determines which bits in the Questionable Condition register will set the corresponding bit in the Questionable Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Questionable Negative Transition by bit

Provides individual bit access to the Questionable Condition Negative Transition register.

Questionable Positive Transition

Determines which bits in the Questionable Condition register will set the corresponding bit in the Questionable Event register, when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Questionable Positive Transition by bit

Provides individual bit access to the Questionable Condition Positive Transition register.

STATus:QUEStionable:OVERload Register

The questionable OVERload register indicates the channels that have raised an overload condition. Reduce the Scale of the Waveform File on the indicated channel.  This is not necessarily an indication of instrument failure.

Questionable OVERload Condition

This query returns the decimal value of the sum of the bits in the Questionable OVERload Condition register.

Questionable OVERload Condition by bit

This query returns the value of the indicated bit in the Questionable OVERload Condition register.

Questionable OVERload Enable

This command determines which bits in the Questionable OVERload Event register will set the Overload Summary bit (bit 1) in the Status Questionable Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Questionable OVERload Enable by bit

This command permits setting or querying and individual bit in the Questionable OVERload Enable register

Questionable OVERload Event Query

This query returns the decimal value of the sum of the bits in the Questionable OVERload Event register.

Questionable OVERload Event Query by bit

This query returns the value of the indicated bit in the Questionable OVERload Event register.

Questionable OVERload Negative Transition

This command determines which bits in the Questionable OVERload Condition register will set the corresponding bit in the Questionable OVERload Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Questionable OVERload Negative Transition by bit

This command provides individual bit access to the Questionable OVERload Condition Negative Transition register.

Questionable OVERload Positive Transition

This command determines which bits in the Questionable OVERload Condition register will set the corresponding bit in the Questionable OVERload Event register when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Questionable OVERload Positive Transition by bit

This command provides individual bit access to the Questionable OVERload Condition Positive Transition register.

STATus:QUEStionable:OVERload:EOVerload Register

The questionable OVERload EOVerload (Extended Overload) register indicates if channels 9 through 16 have raised an overload condition.  Reduce the Scale of the Waveform File on the indicated channel.  This is not necessarily an indication of instrument failure.

Questionable OVERload EOVerload Condition

This query returns the decimal value of the sum of the bits in the Questionable OVERload EOVerload Condition register.

Questionable OVERload EOVerload Condition by bit

This query returns the value of the indicated bit in the Questionable OVERload EOVerload Condition register.

Questionable OVERload EOVerload Enable

This command determines which bits in the Questionable OVERload EOVerload Event register will set the Channels 9 to 16 Summary bit (bit8) in the Status Questionable OVERload Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Questionable OVERload EOVerload Enable by bit

This command permits setting or querying and individual bit in the Questionable OVERload EOVerload Enable register

Questionable OVERload EOVerload Event Query

This query returns the decimal value of the sum of the bits in the Questionable OVERload EOVerload Event register.

Questionable OVERload EOVerload Event Query by bit

This query returns the value of the indicated bit in the Questionable OVERload EOVerload Event register.

Questionable OVERload EOVerload Negative Transition

This command determines which bits in the Questionable OVERload EOVerload Condition register will set the corresponding bit in the Questionable OVERload EOVerload Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Questionable OVERload EOVerload Negative Transition by bit

This command provides individual bit access to the Questionable OVERload EOVerload Condition Negative Transition register.

Questionable OVERload EOVerload Positive Transition

This command determines which bits in the Questionable OVERload EOVerload Condition register will set the corresponding bit in the Questionable OVERload EOVerload Event register when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Questionable OVERload EOVerload Positive Transition by bit

This command provides individual bit access to the Questionable OVERload EOVerload Condition Positive Transition register.

STATus:QUEStionable:POWer Register

The questionable power status register contains information for the amplitude conditions that may bring the instrument’s operation into question.  Typically, a failure in any such action may be restored by examining the instrument’s operation conditions then re-performing the action.  If failures persist, contact Keysight Technologies for support.

Questionable Power Condition

This query returns the decimal value of the sum of the bits in the Questionable Power Condition register.

Questionable Power Condition by bit

This query returns the value of the indicated bit in the Questionable Power Condition register.

Questionable Power Enable

This command determines which bits in the Questionable Power Event register will set the Questionable Power Status Summary bit (bit3) in the Status Questionable Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Questionable Power Enable by bit

This command permits setting or querying and individual bit in the Questionable Power Status register

Questionable Power Event Query

This query returns the decimal value of the sum of the bits in the Questionable Power Event register.

Questionable Power Event Query by bit

This query returns the value of the indicated bit in the Questionable Power Event register.

Questionable Power Negative Transition

This command determines which bits in the Questionable Power Condition register will set the corresponding bit in the Questionable Power Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Questionable Power Negative Transition by bit

This command provides individual bit access to the Questionable Power Condition Negative Transition register.

Questionable Power Positive Transition

This command determines which bits in the Questionable Power Condition register will set the corresponding bit in the Questionable Power Event register when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Questionable Power Positive Transition by bit

This command provides individual bit access to the Questionable Power Condition Positive Transition register.

STATus:QUEStionable:POWer:UNLeveled Register

The questionable power unleveled register indicates the channels that have raised an unleveled condition.  The channel is unable to maintain correct output leveling.  This is not necessarily an indication of instrument failure; unleveled conditions can occur during normal operation.

Questionable Power Unleveled Condition

This query returns the decimal value of the sum of the bits in the Questionable Power Unleveled Condition register.

Questionable Power Unleveled Condition by bit

This query returns the value of the indicated bit in the Questionable Power Unleveled Condition register.

Questionable Power Unleveled Enable

This command determines which bits in the Questionable Power Unleveled Event register will set the Unleveled Summary bit (bit1) in the Status Questionable Calibration Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Questionable Power Unleveled Enable by bit

This command permits setting or querying and individual bit in the Questionable Power Unleveled Enable register

Questionable Power Unleveled Event Query

This query returns the decimal value of the sum of the bits in the Questionable Power Unleveled Event register.

Questionable Power Unleveled Event Query by bit

This query returns the value of the indicated bit in the Questionable Power Unleveled Event register.

Questionable Power Unleveled Negative Transition

This command determines which bits in the Questionable Power Unleveled Condition register will set the corresponding bit in the Questionable Power Unleveled Event register when the condition register bit has a negative transition (1 to 0). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Questionable Power Unleveled Negative Transition by bit

This command provides individual bit access to the Questionable Power Unleveled Condition Negative Transition register.

Questionable Power Unleveled Positive Transition

This command determines which bits in the Questionable Power Unleveled Condition register will set the corresponding bit in the Questionable Power Unleveled Event register when the condition register bit has a positive transition (0 to 1). The variable <integer> is the sum of the decimal values of the bits that you want to enable.

Questionable Power Unleveled Positive Transition by bit

This command provides individual bit access to the Questionable Power Unleveled Condition Positive Transition register.

STATus:QUEStionable:POWer:UNLeveled:EUNLeveled Register

The questionable power unleveled EUNLeveled (Extended Unleveled) register indicates if channels 9 through 16 have raised an unleveled condition.  The channel is unable to maintain correct output leveling.  This is not necessarily an indication of instrument failure; unleveled conditions can occur during normal operation.

Questionable Power Unleveled EUNLeveled Condition

This query returns the decimal value of the sum of the bits in the Questionable Power Unleveled EUNLeveled Condition register.

Questionable Power Unleveled EUNLeveled Condition by bit

This query returns the value of the indicated bit in the Questionable Power Unleveled EUNLeveled Condition register.

Questionable Power Unleveled EUNLeveled Enable

This command determines which bits in the Questionable Power Unleveled EUNLeveled Event register will set the Channels 9 to 16 Summary bit (bit8) in the Status Questionable Power Unleveled Register. The variable <integer> is the sum of the decimal values of the bits you want to enable.

Questionable Power Unleveled EUNLeveled Enable by bit

This command permits setting or querying and individual bit in the Questionable Power Unleveled EUNLeveled Enable register

Questionable Power Unleveled EUNLeveled Event Query

This query returns the decimal value of the sum of the bits in the Questionable Power Unleveled EUNLeveled Event register.