DPCH Synchronization
This topic shows the following:
DPCH Synchronization – Frame Timing Alignment
Figure 1 illustrates the timing alignment for the DPCH channel. There are two possible instrument modes for determining the delay timing of the DPCH Synchronization - Frame Timing Alignment:
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: Frame timing is determined by the External Delay Time.
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: Frame timing is determined by the sum of T0 (1024 chips = the standard timing offset between downlink and uplink), timing offset, and timeslot offset.
Figure 1 DPCH Synchronization - Frame Timing Alignment
DPCH Synchronization – Frame Numbering Alignment
Figure 2 illustrates the frame number alignment for the DPCH channel. The frame number is aligned by the frame synchronization trigger signal from the base station (BTS). When using the frame clock, set the frame clock period to be equal or greater than the longest transport channel TTI period (select 10, 20, 40, or 80 ms). In Figure 2, Reference Measurement Channel 12.2k requires a frame clock of 20 ms or longer to achieve the correct frame number alignment. Using a frame clock of 10 ms would cause an unpredictable frame timing alignment with the transport channel TTI period. Best results are achieved when the frame clock is set to 80 or 2560 ms, or a system frame number reset signal is used.
