Clock/Gate Delay Calibration and BER Test

This procedure requires an E4438C-UN7 (internal bit error rate analyzer).

When clock and gate signals generated by the signal generator are used to perform BER analysis, it is important to realize that the test signal transmitted by the signal generator experiences a propagation delay through the device under test. As a result, the demodulated loopback signal must be realigned in time with the clock and gate signals at the input of the BER analyzer (see figure below). Delay control over the clock and gate signals is provided by the software to enable realignment with the test signal at the input of the BER analyzer.

If the propagation delay characteristics for the device under test are known, enter the delay value in the clock/gate delay field during configuration. The clock and gate signals associated with the waveform will be delayed by the indicated amount during waveform playback. The resolution of the clock/gate delay parameter is directly coupled to the oversampling ratio setting. It can be determined by dividing the symbol period (1 μs) by the oversampling ratio. To increase the incremental delay resolution, increase the oversampling ratio of the configured waveform. When doing so, remember that increasing the oversampling ratio also increases the projected length of the waveform.

If the delay parameter is unknown, leave the default value (0 μs) in the clock/gate delay field and finish configuring the waveform. After the waveform has been calculated, the clock/gate delay calibration utility can be used to determine the delay characteristics of the device under test.

The following example procedure shows how to make clock/gate delay calibration and BER test.

  1. Select Bluetooth Basic Rate + Enhanced Rate from the Format drop-down menu.

  2. Click Licenses in the tree view on the left to ensure that the states for N7606B-R** and N7606B-n** are set to On.

  3. Click Waveform Setup in the tree view.

    Set Marker 1 Source to Symbol Clock.    

    Set Marker 2 Source to Payload Gate.    

  4. Click Packet in the tree view on the left.

    Set Payload Distribution to Multiple Packets.   

     

  5. Click the in the tool bar to generate and download the waveform to the signal generator.

  6. Click Bluetooth 2.1 + EDR in the tree view, then click to configure Clock/Gate Delay Calibration form.

    Set Start to 0.0000 us    

    Set End to 10.0000 us    

    Set Step to 0.1000 us    

    Set Repeat to 2    

  7. Once configured, initiate the BER test sequence by pressing the button. A plot of BER vs. clock/gate delay will be incrementally filled in as each BER test in the sweep is completed. Click button to start delay calibration. When finished, use the arrow buttons to determine the delay value resulting in the lowest bit error rate.

  8. Click and Close Window.

  9. Re-download the waveform and read BER test results from signal generator.