6. AUX IO Global Controls

This property grid category is available only when Capability is set to Real-time Uplink or when Phase Compensation is set to Auto (Real-time) or Manual (Real-time).

Operating Mode

Choice: Multiplexed | Dedicated

Default: Multiplexed

Double-click or use the drop-down menu to select the AUX I/O port operating mode.

Multiplexed − configures the AUX I/O port operating mode to Multiplexed for real-time applications.
Dedicated − configures the AUX I/O port operating mode to Dedicated for real-time applications.

Input Strobe

Choice: Free Run | User

Default: Free Run

Double-click or use the drop-down menu to select the AUX I/O port input strobe. In Dedicated operating mode, the instrument will always be in Free Run mode. If Multiplexed mode is selected, either Free Run or User input strobe mode can be selected.

Free Run − new input data is latched based on an internal clock.
User − a user supplied strobe signal is used to latch data.

Input Strobe Polarity

Choice: Positive | Negative

Default: Positive

Double-click or use the drop-down menu to select the polarity of the user external input strobe signal. This external input strobe signal must be at least 200 ns wide, and user must hold assert 16 input data bits stable 20 ns before the active edge of the user input strobe and hold the data stable for at least 100 ns after the active edge of the user input strobe.

Positive − a rising edge of the external strobe signal will latch the data.
Negative -a falling edge will latch the data.

Output Strobe Polarity

Choice: Positive | Negative

Default: Positive

Double-click or use the drop-down menu to select the polarity of the AUX output sample clock. This signal indicates that the 16 input data bits have been latched and will be output in both Free Run and external input strobe mode. The output pulse will be at least 200 ns wide.

Positive − a pulse with a rising edge will be asserted to indicate when the 16 input data bits have been latched.
Negative -a pulse with a falling edge will be asserted to indicate when the 16 input data bits have been latched.