Clock Adjustment (802.11b/g DSSS/CCK/PBCC)

Default: Refer to DSSS/CCK/PBCC Preset to Standard table

Range: -0.5 to + 0.5 chips

Clock Adjustment determines when the VSA's digital demodulator samples the I/Q trajectory.

The 802.11b/g demodulator used in the VSA does not require symbol-clock timing signals to determine the location of chip detection-decision points. Instead, the demodulator uses an algorithm to determine chip locations.

Some digital communications systems contain non-linearity's that can bias the digital demodulator's estimation of the chip clock position. Use Clock Adjustment to compensate for this "offset" and obtain a lower EVM Error vector magnitude (EVM): A quality metric in digital communication systems. See the EVM metric in the Error Summary Table topic in each demodulator for more information on how EVM is calculated for that modulation format. (Error Vector Magnitude).

The Clock Adjustment (or Offset) is entered in chips. By default, the offset is zero (0) chips. An offset can be specified from -0.5 to +0.5 chips.

The effects of changing Clock Adjustment can be seen by displaying a constellation diagram or eye diagram. Increasing (or decreasing) clock adjustment:

Shifts the detection-decision points in the constellation diagram.
Slides the eye diagram right or left (remember that in the eye diagram, the chip locations remain in a fixed location on the display; therefore, changing the location of chips has the effect of horizontally shifting the eye diagram).

Additional Tips

Here are some additional Tips that may help use Clock Adjustment:

Specifying a Clock Adjustment only affects the I/Q measured trace. It does not affect the I/Q reference trace.
Use the eye diagram with an eye length of one (1) to observe the accuracy of the symbol clock timing. Monitor the EVM (Error Vector Magnitude) in the symbol table summary while adjusting clock adjustment to obtain the optimum symbol timing.

When Preset is selected, Clock Adjustment is reset to 0.0.