These event markers can be configured to output the following marker signals:
Event marker is not used.
Event marker indicates the start of a pulse. A high transition, approximately + 2.5 VDC, indicates the start of a pulse.
Event
marker is present during each pulse in a pattern. A high transition, approximately
+ 2.5 VDC, and time duration slightly longer than
the pulse occurs for each pulse. This marker can be used as a trigger
indicating that a pulse is about to be generated. Note in the 
diagram,
that the pulse gate width is wider than the pulse in the pulse train.
This allows the pulse gate to be used to trigger other devices.
Event marker indicates the first point at the start of a configured signal. A high transition, approximately + 2.5 VDC, indicates the beginning or start of the signal.
Click here to view
the relationship between a pulse train and the marker event
types.
Event delay accuracy is determined by the sampling rate. See Event Delay for more information.
- Event 1 on the rear panel.
- Event 2 on the rear panel.
- Pin #19 of the Auxiliary I/O connector on the rear panel. Can also be used to drive the ALC Hold input (see ALC Hold Line).
- Pin #18 of the Auxiliary I/O connector on the rear panel. Is also routed internally to the pulse modulator.
- Event 1 on the rear panel and pin #1 of the Auxiliary I/O connector on the rear panel.
- Pin #2 of the Auxiliary I/O connector on the rear panel.
- Pin #3 of the Auxiliary I/O connector on the rear panel. Can also be used to drive the ALC Hold input (see ALC Hold Line).
- Pin #4 of the Auxiliary I/O connector on the rear panel. Is also routed internally to the pulse modulator.
- CHANNEL 1 SAMPLE MRK OUT.
- SYNC MRK OUT 1.
- SYNC MRK OUT 2. Can also be used to drive the ALC Hold input of the PSG. (see ALC Hold Line).
- CHANNEL 2 SAMPLE MRK OUT.Must be connected by cable to drive the signal generator pulse modulator.
PSG – Gate/Pulse/Trigger input on the front panel.
ESG – EXT 2 input on the front panel.
MXG/EXG – Pulse input on the rear panel.
- Marker 1 on the front panel.
- Marker 2 on the front panel.
- Marker 3 on the front panel. Can also be used to drive the ALC Hold input of the PSG. (see ALC Hold Line).
- Marker 4 on the front panel. Must be connected by cable to drive the signal generator pulse modulator.
PSG – Gate/Pulse/Trigger input on the front panel.
ESG – EXT 2 input on the front panel.
MXG/EXG – Pulse input on the rear panel.
A
check in this box enables the Event 3 marker signal to drive the ALC Hold
line so that the ALC is active only during the steady state of the pulse
amplitude. Enabling the ALC Hold Line On prevents the ALC from trying to
level the signal during rising or falling edges that are greater than
100 ns, and from trying to level the signal during pulses that have a
power scale other than 0 dB. When ALC Hold
Line On
is on, the Event 3 marker displays ALC Hold, and the drop-down choices are disabled. See Getting Correct Output Power for more information.
Enabling or disabling the ALC Hold Line On requires a download and play to regenerate the correct signal for Event 3.
The Event 3 marker is routed internally to the ALC Hold. Event 3 is also available on pin 19 of the Auxiliary I/O connector on the signal generator's rear panel.
The Event 3 marker is routed internally to the ALC Hold. Event 3 is also available on pin 3 of the Auxiliary I/O connector on the signal generator's rear panel.
The SYNC MRK OUT 2 output is routed externally to the E8267D or N8212A ALC Hold input. The hardware configuration is such that:
The M8190A SYNC MRK OUT 2 output should be connected to the ALC Hold input on the E8267D rear panel or to the ALC Hold input on the N8212A front panel.
Do not connect the external Arb SYNC MRK OUT 2 to the ALC Hold input line unless the ALC Hold Line On is enabled when using an E8267D or N8241A with firmware revisions prior to C.04.71. Do not connect any signals to the ALC Hold input when using the Internal Arb with firmware revisions prior to C.04.71. In either case, the desired RF output signal may not be present depending on the signal present on the ALC Hold input. This problem has been corrected with E8267D or N8212A firmware, release C.04.71. If using firmware release C.04.71 or later, SYNC MRK OUT 2 can be left connected to the ALC Hold input whether the ALC Hold Line On is enabled or not.
The Event 3 marker is routed externally to the E8267D or N8212A ALC Hold input. The hardware configuration is such that:
The N603xA/M933xA or N824xA Marker 3 output should be connected to the ALC Hold input on the E8267D rear panel or to the ALC Hold input on the N8212A front panel.
Do not connect the external Arb Event 3 to the ALC Hold input line unless the ALC Hold Line On is enabled when using an E8267D or N8241A with firmware revisions prior to C.04.71. Do not connect any signals to the ALC Hold input when using the Internal Arb with firmware revisions prior to C.04.71. In either case, the desired RF output signal may not be present depending on the signal present on the ALC Hold input. This problem has been corrected with E8267D or N8212A firmware, release C.04.71. If using firmware release C.04.71 or later, Event 3 can be left connected to the ALC Hold input whether the ALC Hold Line On is enabled or not.
A check in this box enables the Event 4 marker, which provides the correct drive signal to the pulse modulator. Enabling Pulse Modulator On improves the on/off
ratio of the pulse from
approximately 60 dBc to ³80
dBc (or ³64 when using
an ESG ³2.8 GHz). This marker is not user-defined. See Getting Correct Output Power for more information.
Removing the check mark from the check box disables the pulse modulator.
The Event 4 marker is routed internally in the PSG/MXG/EXG/ESG to the pulse modulator, and is also available on pin 18 (PSG/ESG) or pin 4 (MXG/EXG) of the signal generator's rear panel Auxiliary I/O connector. The alignment resolution is 10 ns when using a 100 MHz sample rate.
The Event 4 marker is routed externally to the PSG/MXG/EXG/ESG pulse modulator. The pulse modulation sub system is enabled and the source is set to "Ext Pulse" on the PSG and to "Ext2 DC-Coupled" on the ESG. The hardware configuration is such that:
M8190A CHANNEL 2 SAMPLE MRK OUT should be connected to the "Gate/Pulse/Trigger Input" on the PSG, or to the "Ext 2 Input" on the ESG. The alignment resolution is 250 ps when using a 4 GHz sample rate.
N603xA/M933xA or N824xA Marker 4 output should be connected to the "Gate/Pulse/Trigger Input" on the PSG, or to the "Ext 2 Input" on the ESG. The alignment resolution is 6.4 ns when using a 1.25 GHz sample rate.
