:STATus:TERegister:ENABle

Status Byte Registers Commands

Command Syntax

:STATus:TERegister:ENABle <mask>

<mask> is an integer, 0 to 65535, representing a mask for the bits in the event register.

Query Syntax

:STATus:TERegister:ENABle?

Description

Enters a decimal-weighted value in the enable register that masks the ability to report bits in the Trigger Event Register (see :STATus:TERegister:EVENt?).

Trigger Event Register Commands
Register Read Write Command
Event ♦   :STATus:TERegister:EVENt?
Enable (mask) ♦ ♦ :STATus:TERegister:ENABle
Trigger Event Register Bits
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
Weight		 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1
Event
Register		 — — — — — — — — — — — — — — — TRG
Enable
Register		                                
Sets to Bit 0 (TRG) of Status Byte Register

Bit Definitions

TRG
A true indicates that a hardware trigger has occurred.