FET: Rg, Cgg-Vg Test

Measures the internal gate resistance, Rg, of the device. The device must have a gate oxide. In IC-CAP and the PEMG software the gate resistance is calculated from the Cox, also known as Cgg or Cg. Cgg = Cgs + Cgd + Cgb. Requires the N1272A Device Capacitance Selector SMU.

Used with:

  • B1506A: FET DUT

  • B1505A: FET DUT, CV test type

 

This test requires Rg, Cgg for PowerMOSFET PD1000A.XTD configuration file. See Install PD1000A Configuration Files for more information.

 

Set the test parameters based on the specifications in the device's data sheet:
- If the data sheet lists a maximum test limit for a parameter, use that value.
- If there is no maximum test limit, use a typical value.

See also Setting IV and CV Test Parameters.

Test Schematic

Gate Parameters

Drain Parameters

Example

In this example FET device is used as the example test device.

This device has the following basic characteristics.

  • VDSS: 40 V
  • Rds(on): Typ. 1.35 mΩ @ Vgs=10 V)
  • ID max.: 350A @ 100 μs pulse, VD=10V, 1390 A @ Vd=2.5 V
  • Coss: 2360 pF typ. @ Vd=25 V
  • Rg(int): 6.8 Ω typ.

Setup

  1. Choose FET as device type.
  2. Select the checkbox for Rg, Cgg-Vg test.

General settings

  1. Set 1 MHz as measurement frequency

Gate Voltage Sweep

  1. Leave as initial settings (-3 V to 3 V, LinearSingle)

Collector / Drain Voltage Bias

  1. Leave as an initial setting (0 V).

Click the Start button

The Rg is measured immediately at VGS = 0 V is 5.48 Ω.