This dialog is used to set many IF receiver settings for models.
In this topic:
Wideband/Normal IF path:
Note: For the following discussion, RF = Receiver Frequency
With DSP Version 4:
RF < 53 MHz: IF = 2.535211 MHz [3 x (60e6 / 71)]
RF >= 53 MHz: IF = 7.605634 MHz [9 x (60e6 / 71)]
With DSP Version 5, the IF frequency is dependent on the RF AND the current IFBW setting:
All RF; IF Bandwidth >= 1MHz: (All Models)
IFBW |
IF |
1 MHz |
7.692 MHz |
1.5 MHz |
7.368 MHz |
2 MHz |
8.450 MHz |
3 MHz |
8.163 MHz |
5 MHz |
6.897 MHz |
7 MHz |
10.53 MHz |
10 MHz |
15.38 MHz |
15 MHz |
22.22 MHZ |
IF Bandwidth <= 600 kHz:
RF >= 53 MHz; All models: IF = 7.438017 MHz [(9 x (100e6 / 121)]
RF <= 53 MHz; PNA-X models: IF = 2.479339 MHz [(3 x (100e6 / 121)]
RF <= 53 MHz; N522xB models: IF = 826.446 kHz [1 x (100e6 / 121)]
Narrowband IF path:
IF = 10.70 MHz
Bandwidth = 30 kHz
Note: The IFBW is limited to 600 kHz when performing Swept IMD measurements even if the Wide IF path is selected.
The IF frequency can be changed to any value between +14.9999 MHz and -14.9999 MHz using SENS:IF:FREQ or IFFrequency commands.
With DSP Version 4 - 34 and above, min and max IF frequencies up to +/- 20.1 MHz are available.
With DSP Version 5, min and max IF frequencies up to +/- 38 MHz are available.
Performance is degraded drastically above +/- 14.9999 MHz.
The IF path, represented in the block diagram at the top of the dialog, is duplicated for each of the receivers (A, B, C, D, R1, R2, R3, R4). In addition, each path can be configured differently for each channel.
Element - Indicates an element in the expanded block diagram. IF Input (1) - Available on the PNA-X and N522xB with Opt 020. Internal input is a test port or reference receiver input. External Input is through the PNA-X and N522xB rear-panel connectors. IF Attenuator (3) - Specify IF attenuation for the narrowband path of the selected receiver. IF Filter (2) - Select Wideband or Narrowband (includes the ability to pulse gates). IF Gain (10)- Set to Auto by default, the following are reasons to change the IF Gain:
ADC Filter (5) - Select Auto, Narrow (9 MHz or 11 MHz), or Wide (16 MHz or 38 MHz) filter. Learn more. Couple all IF paths - Check to make the same setting for all receivers. |
Blue boxes
are configurable elements.
Click a blue box, or scroll down, to see how to make settings using SCPI
and COM
commands.
Scroll up for descriptions of the Receiver / IF Paths blocks. Most of these elements can be set from the front-panel User Interface (UI).
ADC: (Analog to Digital Converter) This block, responsible for quantifying receiver measurements, is triggered when BOTH the Meas Trig line AND P0 pulse generator line are TRUE. In addition, the Meas Trig signal MUST be TRUE before or at the same time as the P0 signal.
Meas Trig Signal
When VNA Trigger source is set to Internal, the Meas Trig line is ALWAYS TRUE. Internal trigger source is the best setting for making Pulse measurements. This means that the P0 line determines when pulse measurements are made.
When VNA Trigger source is set to External, the Meas Trig line can be configured from the Meas Trig (External) dialog.
P0 (Trig) Signal - See below.
See how to make these settings remotely
Switch 6: Represents Internal or External triggering for the pulse generator. This setting, and the External Trigger Pulse settings, are made on the Trigger dialog, Pulse Trigger tab.
On the Integrated Pulse App, Pulse Setup dialog, when Pulse Trigger source is set to External, then External is selected automatically in the Pulse Gen dialog.
Internal - The pulse generator is internally triggered and puts out a periodic pulse train with a period defined by the pulse generator settings.
External - The pulse period is ignored, and the pulse generator puts out one set of pulses (P0-P4) per external trigger. All five pulse outputs have unique delay and pulse width settings.
External trigger input is on the Pulse I/O connector pin 7 (PulseSyncIn). The PulseSyncIn line provides a trigger signal into the Pulse Generators. If a level trigger is still valid when the first set of pulses is finished, another set will be generated. Only one set of pulses is emitted when edge triggering is used.
The External pulse input polarity (positive or negative) and type (edge or level) is configurable only with DSP version: 4.0 FPGA: 34 or higher. Learn more. Otherwise, the pulse generators respond only to positive, level input trigger signals.
P0: When P0 is enabled, it is hardwired to trigger the data acquisition ADCs. See ADC (above).
If the data acquisition system is not ready (Meas Trig = NOT TRIGGERED), the P0 trigger is ignored.
If the pulse generator is internally triggered, then the data acquisition system receives periodic triggers.
If the pulse generator is externally triggered, then the data acquisition system receives a trigger each time the pulse generator is triggered.
Data acquisition is synchronized to the pulse generator ONLY when P0 is enabled. This is equivalent to enabling Synchronize ADCs using pulse trigger on the Pulse Generators Setup dialog. Data acquisition begins on the rising edge of P0. The width of P0 does NOT directly matter as data acquisition does not stop when P0 goes false. The following describes how the P0 generator triggers data acquisition:
Step mode sweeps of any sweep type: By default, each P0 rising edge triggers a single data point. When point averaging is on, all of the measurements (subpoints) that are required to average each point are made with a single trigger. To individually trigger the acquisition of each subpoint, send the subPointTrigger (SCPI or COM) command.
CW sweeps: Each trigger initiates acquisition for the entire sweep. This is currently used for wideband pulse profiling.
P1 thru P4 These four pulse generator outputs are hardwired to rear panel outputs on the Pulse I/O connector (pins 10 - 13). They are also routed to two switches (#4 and #7 on the above diagram) along with the following three lines:
Rear Panel External pulse generator input from Pulse I/O connector pin 8 (RFPulseModIn).
OFF Pulse is constantly in LOW state causing gate and source to be OFF.
ON Pulse is constantly in HIGH state causing gate and source to be ON.
Switch 7 Pulse Modulation - 1 of 7 lines to each of the sources. Important: When internally modulating the sources, source leveling must be set to Open-loop.
Rear-panel Outputs: Pulse I/O connector (pins 10 - 13) hardwired.
Source1 and Source2 pulse modulators: (#8 and #9 on the above diagram)
Filters the ADC (digital) output from top block and outputs data to the VNA display.
Most of the following elements, highlighted in BLUE in the above Block Diagram, have settings that are made using SCPI or COM commands. In general, the command specifies an element name and a setting.
See COM object and example.
These are the same commands that are used to make settings in the RF Path Configurator.
Ref# |
Element Name Description |
Settings |
"IFSWn" For 2-port PNA-X and N522x, n = A, B, R1, R2 For 4-port PNA-X and N522x, n = A, B, C, D, R (for R1 to R4) For example: "IFSWB" Requires Opt 020 external IF inputs on the rear panel |
"Internal" "External" Rear Panel IF connectors. 4-port use R for Ref 1 to 4 |
|
"IFPathn" For 2-port PNA-X and N522x, n = A, B, R1, R2 For 4-port PNA-X and N522x, n = A, B, C, D, R1, R2, R3, R4 "IFSigPathAll" makes setting for ALL receivers. |
"WBF" Wide Band Filter Path (default) "NBF" Narrow Band Filter Path |
|
"NBFATNn" For 2-port PNA-X and N522x, n = A, B, R1, R2 For 4-port PNA-X and N522x, n = A, B, C, D, R1, R2, R3, R4 For example: "NBFATNB" |
0 to 31 in 1 dB steps For example: "28" |
|
"IFGaten" For 2-port PNA-X and N522x, n = A, B, R1, R2 For 4-port PNA-X and N522x, n = A, B, C, D, R1, R2, R3, R4 For example: "IFGateB" |
"On" Gate is always ON "Off" Gate is always OFF "RearPanel" (use Pulse IO pins 1 to 5) "Pulse1" "Pulse2" "Pulse3" "Pulse4" |
|
"IFAntiAliasFilter"
|
"Auto" VNA selects which filter to use based on other IF settings. "Narrow" Sets 9 MHz for DSP Version 4 Sets 11 MHz for DSP Version 5 "Wide" Sets 16 MHz for DSP Version 4 Sets 38 MHz for DSP Version 5 "9MHZ" is Superseded - Use "Narrow". "16MHZ" is Superseded - Use "Wide". |
|
"PulseTrigInput" Requires Opt S93025A/B - Four Internal Pulse Generators |
"Internal" Internal Pulse In - pulse generators are triggered each period. "External" External Pulse Synch In -Pulse I/O pin 7) - An external trigger signal is required to trigger the pulse generators for each pulse. <name> An external pulse generator to be configured as the Primary Pulse Trigger. |
|
"PulseModDrive" Select from 1 of 7 lines to modulate the OUT1 path of Sources 1 and 2 . Important: When Pulse 1-4 is selected to modulate the sources, source leveling must be set to Open-loop. |
"On" Pulse Mod drive is always ON, leaving "SRC1|2 Out 1" ON and not modulated. Default setting. "Off" Pulse Mod drive is always OFF, leaving "SRC1|2 Out 1" OFF. "RearPanel" (use Pulse IO pin 8) "Pulse1" "Pulse2" "Pulse3" "Pulse4" |
|
"Src1Out1PulseModEnable" Requires Opt 021 - Source1 Pulse Modulator |
"Enable" "Disable" |
|
"Src2Out1PulseModEnable" Requires Opt 022 - Source2 Pulse Modulator |
"Enable" "Disable" |
|
"IFGAIN""n For 2-port models, n = A, B, R1, R2 For 4-port models, n = A, B, C, D, R1, R2, R3, R4 For example: "IFGAINB" |
"0", "2", "4", "6", "8","10", "11", "13", "15", "Auto" |