Uplink Closed Loop Power Control Parameters and UE Target Power

UL CL Power Control Mode

UL CL Power Ctrl Mode controls what power control bit pattern is sent to the UE. It can be set to the following:

• Active bits - the test set sends the power control bits required to maintain the UE's DPDCH+DPCCH power at the value entered for UE Target Power . Note that when on an HSDPA or HSPA connection, the UE's total output power will be greater than this value when power is present in the uplink HS-DPCCH. See UE Target Power for additional information.
  When UL CL Power Control Mode is set to Active bits , the test set measures the UE's DPCCH level and uses the uplink Beta _c and Beta _d values (see Uplink DPCH Bc/Bd Control ) to determine what power control bits to send to the UE to drive its DPDCH+DPCCH power to the UE Target Power (for UL CL Power Ctrl Algorithm = Two , the test set does not order the UE to change its power unless its power is more than +/- 0.75 dB away from UE Target Power ).
• Alternating bits - the test set sends alternating power-up and power-down bits to the UE. When UL CL Power Ctrl Algorithm is set to Two , the UE is thus instructed to transmit at a fixed power level (the power level at which it was transmitting when Alternating bits was activated). When UL CL Power Ctrl Algorithm is set to One , the UE is thus instructed to vary its power around the power level at which it was transmitting when Alternating bits was activated by 1 or 2 dB (depending upon the UL CL Power Ctrl Stepsize setting). When in Alternating bits mode, you can instruct the UE to increase or decrease its transmit power level by 1 dB using the Send Step Up TPC Bit Pattern or Send Step Down TPC Bit Pattern commands (see Send Step Up/Down TPC Bit Pattern ).
• All Up bits - the test set sends a continuous pattern of power-up bits. This is often used to drive the UE to transmit at its maximum power level. Note, the test set will continuously send up bits to the UE in this mode, even if the UE exceeds the test set's specified measurement limit of +28 dBm.
• All Down bits - the test set sends a continuous pattern of power-down bits. This is often used to drive the UE to transmit at its minimum power level.
• 10 Up/Down bits - the test set sends a repeating pattern of 10 power-up bits and 10 power-down bits. The pattern always begins on a frame boundary.

GPIB commands: CALL[:CELL]:CLPControl:UPLink:MODE and CALL:FDDTest:CLPControl:UPLink:MODE .

UL CL Power Ctrl Algorithm

UL CL Power Ctrl Algorithm specifies which power control algorithm the UE should use while under closed loop power control (see 3GPP TS 25.214 5.1.2.2.1). The power control algorithm determines the method the UE uses to derive a single TPC_cmd for each slot from the TPC commands received from the test set. See UL CL Power Ctrl Stepsize for information regarding how TPC_cmd is then translated into a UE transmit power change.

UL CL Power Ctrl Algorithm can be set to:

• One - When using power control algorithm one to process TPC commands, the UE determines TPC_cmd for each slot based on the TPC commands received in that slot (if the UE is in soft handover, it will receive more than one TPC command in each slot).

  If only one TPC command is received in the slot and is equal to 0, then TPC_cmd for that slot is -1. If only one TPC command is received in the slot and is equal to 1, then TPC_cmd for that slot is 1. (See 3GPP TS 25.214 5.1.2.2.2 for more information about how the UE combines TPC commands received in a slot.) The UE then uses the UL CL Power Ctrl Stepsize value to determine whether to change its power by a magnitude of 1 or 2 dB.

  Note, some measurements may give unexpected results when the UE is using power control algorithm one, because power control algorithm one may cause the UE's output power to change during the measurement interval.

• Two - When using power control algorithm two to process TPC commands, the UE processes TPC commands on a 5-slot cycle, where the set of 5 slots is aligned to a frame boundary.

  If only one TPC command is received in each slot, TPC_cmd is derived as follows: TPC_cmd for the first 4 slots in the 5-slot set is always 0. For the fifth slot in the set, TPC_cmd is 1 if the TPC commands for all 5 slots are 1, is -1 if the TPC commands for all 5 slots are 0, or is 0 otherwise. The change in power is always 0 or of magnitude 1 dB.

This setting can only be changed while in Idle state. To change the power control step size while on a connection, you must perform a Physical Channel Reconfiguration . After completion of the Physical Channel Reconfiguration procedure, successful or not, the UL CL Power Ctrl Algorithm setting is overwritten with the value of Handover UL CL Power Ctrl Algorithm .

This setting applies to both cell 1 and cell 2 (for the lab application only).

GPIB commands: CALL[:CELL]:CLPControl:UPLink:ALGorithm and CALL:FDDTest:CLPControl:UPLink:ALGorithm .

UL CL Power Ctrl Stepsize

When UL CL Power Ctrl Algorithm is set to One , you can specify the size of the change in UE power for each TPC_cmd. You can set UL CL Power Ctrl Stepsize to 1 dB or 2 dB, which sets Delta _TPC to 1 dB or 2 dB, respectively. For algorithm two, Delta _TPC is always set to 1 dB.

The UE determines its required change in output power by multiplying Delta _TPC by TPC_cmd. The change in power is applied in the slot adjacent to the slot in which TPC_cmd was received.

This setting can only be changed in Idle state, and when UL CL Power Ctrl Stepsize is set to One . To change the power control step size while on a connection, you must perform a Physical Channel Reconfiguration . After completion of the Physical Channel Reconfiguration procedure, successful or not, the UL CL Power Ctrl Step Size setting is overwritten with the value of Handover UL CL Power Ctrl Step Size .

If UL CL Power Ctrl Stepsize is set to Two , this setting is returned to its default value of 1 dB .

This setting applies to both cell 1 and cell 2 (cell 2 is present in the lab application only).

GPIB command: CALL[:CELL]:CLPControl:UPLink:STEPsize .

Cell 2 UL CL Power Ctrl Mode

For the lab application only, the test set can send power control bit patterns to the UE on cell 2. The same modes are available as the UL CL Power Control Mode setting.

When Cell 2 Power Ctrl is set to Active bits , the same power control bits are sent on the cell 1 DPCCH and the cell 2 DPCCH.

See Cell 2 Overview .

GPIB command: CALL:CELL2:CLPControl .