*SRE (Service Request Enable)

Command Syntax

*SRE <mask>

<mask> is an integer, 0 to 255, representing a mask for the bits in the event register.

Query Syntax

*SRE?

Description

Enters a decimal-weighted value in the service request enable register that masks the ability to report bits in the status byte event register. To read the status byte register, use the *STB common command. By setting the *SRE, when the event happens, you have enabled the FlexDCA's interrupt capability. FlexDCA will then do an SRQ (service request), which is an interrupt. The Service Request Enable Register contains a mask value for the bits to be enabled in the Status Byte Register. A "1" in the Service Request Enable Register enables the corresponding bit in the Status Byte Register. A "0" disables the bit.

Status Byte Register Commands

Register	Read	Write	Command
Event	♦		*STB?
Enable (mask)	♦	♦	*SRE

Status Byte Registers

Bit	7	6	5	4	3	2	1	0
Bit Weight	128	64	32	16	8	4	2	1
Event Register	OPER	RQS/MSS	ESB	MAV	—	MSG	USR	TRG
Enable Register
Sets	Sends a service request interrupt (SRQ) to the controller.

Bit Definitions

TRG

A true indicates that a trigger has occurred. This bit is set by the Trigger Event Register.

USR

A true indicates that an enabled user event condition has occurred. This bit is set by the User Event Register.

MSG

A true indicates that a message has been displayed and that the message queue has at least one entry. This bit is set by the Message Event Register.

MAV

A true indicates that an output message is ready.

ESB

A true indicates that an enabled event status condition occurred. This bit is set by the Standard Event Register.

RQS/MSS

A true indicates that FlexDCA has requesting service.

OPER

A true indicates that enabled operation status conditions have occurred. This bit is set by the Operation Event Register.