*STB? (Status Byte)

Query Syntax

*STB?

Description

Reads the Status Byte event register (including the Main Summary Status, MSS, bit) to determine the status of individual status bits. The decimal-weighted value of the register is returned. Reporting of event register bits in the status register system is controlled by the mask loaded into the enable register. All true event bits, that are enabled, are logically "AND"ed, which results in a service request interrupt (SRQ) to the controller. In response to a serial poll (SPOLL), Request Service (RQS) is reported on bit 6 of the status byte. Otherwise, the Main Summary Status bit (MSS) is reported on bit 6. MSS is the inclusive OR of the bitwise combination, excluding bit 6, of the Status Byte Register and the Service Request Enable Register. The MSS message indicates that the scope is requesting service (SRQ).

To enter a mask into the enable register, use the *SRE common command.

Status Byte Register Commands

Register	Read	Write	Command
Event	♦		*STB?
Enable (mask)	♦	♦	*SRE

Status Byte Registers

Bit	7	6	5	4	3	2	1	0
Bit Weight	128	64	32	16	8	4	2	1
Event Register	OPER	RQS/MSS	ESB	MAV	—	MSG	USR	TRG
Enable Register
Sets	Sends a service request interrupt (SRQ) to the controller.

Bit Definitions

TRG

A true indicates that a trigger has occurred. This bit is set by the Trigger Event Register.

USR

A true indicates that an enabled user event condition has occurred. This bit is set by the User Event Register.

MSG

A true indicates that a message has been displayed and that the message queue has at least one entry. This bit is set by the Message Event Register.

MAV

A true indicates that an output message is ready.

ESB

A true indicates that an enabled event status condition occurred. This bit is set by the Standard Event Register.

RQS/MSS

A true indicates that FlexDCA has requesting service.

OPER

A true indicates that enabled operation status conditions have occurred. This bit is set by the Operation Event Register.