86108A Module Specifications
Instrument:
N1000A
DCA-X
FlexDCA Rev:
N1000A: ≥A.06.00
86100D: ≤A.07.60
Availability:
Obsolete
86108A module specifications and characteristics apply when a module is installed in the instrument mainframe. The following notes refer to the module specifications listed in this chapter.
All specifications describe warranted performance over the temperature range +10° C to + 40° C (unless otherwise noted). The specifications are applicable after the temperature is stabilized, which occurs after 1 hour of continuous operation and while module calibration is valid. Many performance parameters are enhanced through frequent, simple user calibrations.
Specifications describe warranted performance. Characteristics provide useful, nonwarranted information about the functions and performance of the instrument. Characteristics are printed in green italics.
Factory Calibration Cycle. For optimum performance, the instrument should have a complete verification of specifications once every 12 months.
Nominal Value indicates the expected, but not warranted, value of the parameter.
| Item | Description |
|---|---|
| Bandwidth | 16 GHz, characteristic and 32 GHz (35 GHz characteristic) |
| Derived from time domain analysis. | |
| Transition time (10% to 90%, calculated from TR = 0.35/BW) | 10 ps (characteristic) |
| RMS noise | |
| Characteristic | 240 μV (16 GHz) 420 μV (32 GHz) |
| Maximum | 350 μV (16 GHz) 700 μV (32 GHz) |
| Scale Factor (per division) | |
| Minimum | 2 mV/division |
| Maximum | 100 mV/division |
| DC accuracy (single marker) | ±0.7% of full scale ±2 mV ± 1.5% of (reading – channel offset) (16 GHz) ±0.7% of full scale ±2 mV ± 3% of (reading – channel offset) (32 GHz) |
| CW offset range (referenced from center of screen) | ±500 mV |
| Input dynamic range (relative to channel offset) | ±400 mV |
| Maximum input signal | ± 2 Vdc (+16 dBm) |
| Characteristic jitter (clock recovery and precision timebase configuration) | < 60 fs (characteristic) |
| Verified with maximum input signal (approximately 800 mVpp) | |
| Maximum jitter (clock recovery and precision timebase configuration) | < 90 fs |
| Verified with maximum input signal (approximately 800 mVpp) | |
| Characteristic jitter (clock recovery without precision timebase active) | < 1.25 ps (characteristic) |
| Effective trigger-to-sample delay (clock recovery and precision timebase configuration) | < 200 ps characteristic) |
| Characteristic jitter (trigger signal applied to precision timebase input) | < 60 fs (characteristic) |
| Verified with maximum input signal (approximately 800 mVpp) | |
| Maximum jitter (trigger signal applied to precision timebase input) | < 90 fs |
| Verified with maximum input signal (approximately 800 mVpp) | |
| Precision timebase reference input | 2 to 13.5 GHz 1 to 18 GHz (characteristic) |
| Precision timebase reference input amplitude | 1.0 to 1.6 Vpp (characteristic) |
| Precision timebase input signal type The precision timebase performs optimally with a sinusoidal input. Non-sinusoidal signals will operate with some degradation in timebase linearity. | Sinusoid |
| Precision timebase maximum input level | ±2V (16 dBm) |
| Precision timebase maximum DC offset level | ±200 mV |
| Precision timebase input impedance | 50 ohm |
| Precision timebase connector type | 3.5 mm male |
| Timebase resolution (with precision timebase active) | 0.5 ps/div |
| Timebase resolution (precision timebase disabled) | 2 ps/div |
| Nominal impedance | 50 ohm |
| Reflections (for 30 ps rise time) | 5% |
| Electrical Input | 3.5 mm (male) |
| CH1 to CH2 skew | < 12 ps (characteristic) |
| Item | Description |
|---|---|
| Data rates input range | Continuous tuning 0.05 to 14.2 Gb/s |
| Clock frequency input range | Continuous tuning 0.025 to 7.10 GHz |
| Minimum input level to acquire lock | 175 mVpp |
| Recovered clock random jitter Used as internal trigger or at clock output port. This is not taking advantage of the 86108A precision timebase. With precision timebase enabled, system jitter approaches 60 fs for best performance. At 7.1 Gb/s residual jitter is approximately 700 fs. | < 500 fs @ 2 Gb/s < 400 fs @ 5 Gb/s < 400 fs @ 10 Gb/s |
| Clock recovery adjustable loop bandwidth range (user selectable) | 0.015 to 10 MHz |
| Clock recovery loop peaking range | Up to 4 settings (dependent on loop BW) |
| Loop bandwidth accuracy | ± 30%, characteristic |
| Tracking range (includes spread-spectrum tracking) | ± 2500 ppm ± 0.25%, characteristic |
| Acquisition range | ± 5000 ppm, characteristic |
| Maximum consecutive identical digits to lock | 150, characteristic |
| Auto relocking | If signal lock is lost, system can automatically attempt to regain phase-lock. User selectable to enable or disable. |
| Residual spread spectrum | –72 ±3 dB @ 33 kHz, characteristic |
| Front panel recovered clock amplitude | 0.15 to 1.0 Vpp (0.3 to 1.0 Vpp, characteristic) |
| Front panel recovered clock divide ratio (user selectable) | 8:1 (x8), 4:1 (x4), 2:1 (x2), 1:1, 1:2, 1:4, 1:8, 1:16, 1:32 Ratios 8:1, 4:1, 2:1, and 1:32 require firmware revision A.10.50. |
| Rear panel recovered clock divide ratio (user selectable) | 1, 2, 4, 8, 16 |
| Recovered clock front panel connector type | SMA |
| Internal frequency counter accuracy | ± 10 ppm |