:STATus:TRIGger:ENABle
Command Syntax
:STATus:TRIGger:ENABle <mask>
<mask> is an integer, 0 to 65535, representing a mask for the bits in the event register.
Query Syntax
:STATus:TRIGger:ENABle?
Description
Enters a decimal-weighted value in the enable register that masks the ability to report bits in the Trigger Event Register (see :STATus:TRIGger:EVENt?).
| Register | Read | Write | Command |
|---|---|---|---|
| Event | ♦ | :STATus:TRIGger:EVENt? | |
| Enable (mask) | ♦ | ♦ | :STATus:TRIGger:ENABle |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Bit Weight |
32768 | 16384 | 8192 | 4096 | 2048 | 1024 | 512 | 256 | 128 | 64 | 32 | 16 | 8 | 4 | 2 | 1 |
| Event Register |
— | — | — | — | — | — | — | — | — | — | — | — | — | STER | ATER | AER |
| Enable Register |
||||||||||||||||
| Sets |
 to Bit 5 (AER) of Operation Status Register |
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Bit Definitions
- STER
- A true indicates that a software (qualified) trigger has occurred.
- ATER
- When trigger sweep is set to Auto, a true indicates the wait period for a valid hardware or software (qualified) trigger has elapsed and an auto trigger has occurred.
- AER
- A true indicates that hardware is armed and ready to trigger.