:STATus:LTESt:ENABle

Operation Status Registers Commands

Command Syntax

:STATus:LTESt:ENABle <mask>

<mask> is an integer, 0 to 65535, representing a mask for the bits in the event register.

Query Syntax

:STATus:LTESt:ENABle?

Description

Enters a decimal-weighted value in the limit test enable register that masks the ability to report bits in the limit test event register.

Limit Test Register Commands
Register Read Write Command
Event ♦   :STATus:LTESt:EVENt?
Enable (mask) ♦ ♦ :STATus:LTESt:ENABle
Limit Test Status Register Bits
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
Weight		 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1
Event
Register		 — — — — — — — — — — — — LLINE MTEST ACQ MEAS
Enable
Register		                                
Sets to Bit 9 (LTEST) of Operation Status Register

Bit Definitions

LLINE
A true indicates that a limit-line test has completed. Use the :LLINe Subsystem to configure a limit-line-based limit test.
MTEST
A true indicates that the mask test limit test has completed. Use the :LTESt:MTESt:MRESult{N}:STATe command to configure a mask limit test.
ACQ
A true indicates that the specified number of waveforms, samples, or patterns has occurred (acquisition limit test has completed). Use the :LTESt:ACQuire:STATe command to configure an acquisition limit test.
MEAS
A true indicates that the measurements limit test has completed. Use the :LTESt:MEASure:MLIMit:STATe command to configure a measurements limit test.