:STATus:LLINE:EVENt?
Instrument:
N1010A
N1000A
DCA-M
Meas. mode:
Scope
Eye
Jitter
TDR
Flex Apps:
FlexDCA
FlexRT
Query Syntax
:STATus:LLINE:EVENt?
Description
Reads the limit line event register to determine the status of individual status bits. The decimal-weighted value of the register is returned. The only bit used is bit 0 (COMP), which indicated if a limit-line-based limit test has completed. Reporting of event register bits in the status register system is controlled by the mask loaded into the enable register. All true event bits, that are enabled, are logically AND'ed, which results in setting true bit 5 (LLINE) of the Operation Status Register. Use the :LLINe subsystem to configure a limit-line-based limit test.
| Register | Read | Write | Command |
|---|---|---|---|
| Event | ♦ | :STATus:LLINE:EVENt? | |
| Enable (mask) | ♦ | ♦ | :STATus:LLINE:ENABle |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
| Bit Weight |
128 | 64 | 32 | 16 | 8 | 4 | 2 | 1 |
| Event Register |
— | — | — | — | — | — | — | COMP |
| Enable Register |
||||||||
| Sets |
 to Bit 5 (LLINE) of Operation Status Register |
|||||||
Bit Definitions
- COMP
- A true indicates that a limit-line test has completed.