:STATus:ACQuisition:EVENt?

Query Syntax

:STATus:ACQuisition:EVENt?

Description

Reads the acquisition event register to determine the status of individual status bits. The decimal-weighted value of the register is returned. The only bit used is bit 0 (COMP), which indicates if an acquisition limit test has completed with the specified number of waveforms, samples, or patterns. Reporting of event register bits in the status register system is controlled by the mask loaded into the enable register. All true event bits, that are enabled, are logically AND'ed, which results in setting true bit 9 (ACQ) of the Operation Status Register. Upon successful completion of the test, bit 0 (COMP) in the limit-test event register will also be set. Use the :LTESt:ACQuire:STATe command to configure a limit test.

Acquisition Register Commands

Register	Read	Write	Command
Event	♦		:STATus:ACQuisition:EVENt?
Enable (mask)	♦	♦	:STATus:ACQuisition:ENABle

Acquisition Status Registers

Bit	7	6	5	4	3	2	1	0
Bit Weight	128	64	32	16	8	4	2	1
Event Register	—	—	—	—	—	—	—	COMP
Enable Register
Sets	to Bit 9 (ACQ) of Operation Status Register

Bit Definitions

COMP

A true indicates that the specified number of waveforms, samples, or patterns has occurred.