:STATus:MTESt:EVENt?
Instrument:
N1010A
N1000A
DCA-M
Meas. mode:
Scope
Eye
Jitter
TDR
Flex Apps:
FlexDCA
FlexRT
Query Syntax
:STATus:MTESt:EVENt?
Description
Reads the mask test event register to determine the status of individual status bits. The decimal-weighted value of the register is returned. The only bit used is bit 0 (COMP), which indicates if an mask limit test has completed. Reporting of event register bits in the status register system is controlled by the mask loaded into the enable register. All true event bits, that are enabled, are logically AND'ed, which results in setting true bit 10 (MTEST) of the Operation Status Register. Use the :LTESt:MTESt:STATE command to configure a mask limit test.
| Register | Read | Write | Command |
|---|---|---|---|
| Event | ♦ | :STATus:MTESt:EVENt? | |
| Enable (mask) | ♦ | ♦ | :STATus:MTESt:ENABle |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
| Bit Weight |
128 | 64 | 32 | 16 | 8 | 4 | 2 | 1 |
| Event Register |
— | — | — | — | — | — | — | COMP |
| Enable Register |
||||||||
| Sets |
 to Bit 10 (MTEST) of Operation Status Register |
|||||||
Bit Definitions
- COMP
- A true indicates that the mask test has completed.