:CRECovery Subsystem
The Clock Recovery subsystem commands control the clock recovery modules. This includes setting data rates, as well as querying lock status and "signal present" conditions. Be sure to include the module slot number in the command. For the 86108A/B, only slot 1 is allowed. For 83496A/B clock recovery modules, the slot number can be 1 or 3 depending on the location of the module in the DCA-X's module bay. For the N107x-series clock recovery DCA-Ms, the slot number can be 1 through 8.
The JSA commands configure the JSA's clock-recovery emulation. To save JSA data to a file, use the :DISK:JSANalysis:SAVE command. To load a JSA data file into JSA memory, use the :DISK:JSANalysis:RECall command. To use the JSA memory, use the :JSAMemory subsystem commands. Use the :CRECovery1:JSANalysis:ACQuire command to turn on jitter spectrum analysis.
JSA requires an N107x-series DCA-M module or an 86108A/B module. Option JSA must be on the module. To use JSA in Jitter Mode, N1000A Option 200 Enhanced Jitter Analysis or N1010A Option 200 Enhanced Jitter Analysis is required.
Not all of this subsystem commands apply to every module, as the following table shows. Depending on the module, the data rates can either be set to a specific value or to any value within a range, as listed in the Data Rate Table.
JSA requires an N1076A, N1076B, N1077A, N1078A, or 86108A/B module with Option JSA. To use JSA in Jitter Mode, N1000A Option 200 Enhanced Jitter Analysis or N1010A Option 200 Enhanced Jitter Analysis is required.
| Command | N107x-Series DCA-M |
N4877A | 86108A/B | 83496A/B | |
|---|---|---|---|---|---|
| Standard | Opt. 300 | ||||
| ACDRate? | Queries if continuous (as opposed to discrete) data rate settings supported? | ||||
| ♦ | ♦ | ♦ | ♦ | ||
| ACLBandwidth? | Queries if continuous (as opposed to discrete) loop bandwidth settings supported? | ||||
| ♦ | ♦ | ♦ | ♦ | ||
| ADRatio? | Returns the auxiliary clock divide output ratio for the front-panel Aux Clock Output. | ||||
| ♦ | |||||
| CFRequency? | Returns frequency of recovered data clock of 86108A/B modules. | ||||
| ♦ | ♦ | ♦ | |||
| CLBandwidth | Sets the PLL's loop bandwidth. | ||||
| ♦ | ♦ | ♦ | |||
| CRATe | Sets the input data rate. | ||||
| ♦ | ♦ | ♦ | ♦ | ♦ | |
| EHGain | Turns on and off the N1078A Enable High Gain setting. | ||||
| ♦ | |||||
| ELEVel | Fine tunes the equalization level on the PLL loop characteristics for clock recovery. | ||||
| ♦ | |||||
| LBANdwidth | Sets the PLL's loop bandwidth. | ||||
| ♦ | ♦ | ♦ | |||
| LBWMode | Sets the PLL's loop-bandwidth entry mode. | ||||
| ♦ | ♦ | ♦ | |||
| LOCKed? | Returns the locked status of the clock recovery module. | ||||
| ♦ | ♦ | ♦ | ♦ | ||
| LSELect | Selects the PLL's Type-2 loop transition frequency (peaking). | ||||
| ♦ | ♦ | ||||
| LSELect:AUTomatic | Turns on automatic selection of the Type-2 loop transition frequency (peaking). | ||||
| ♦ | ♦ | ♦ | |||
| ODRatio | Sets the output clock divide ratio (Recovered Clock Out). | ||||
| ♦ | ♦ | ♦ | ♦ | ♦ | |
| ODRatio:AUTO | Turns on automatic selection of front-panel output clock divide ratio. | ||||
| ♦ | ♦ | ♦ | ♦ | ♦ | |
| OUTPut:DMODe | Swaps data routed to the front-panel DEMUX DATA output ports. | ||||
| ♦ | |||||
| PRESets | Loads saved or factory provided clock recovery settings. | ||||
| ♦ | |||||
| PRESets:SELections? | Returns list of all available clock recovery presets. | ||||
| ♦ | |||||
| RATE | Sets the input signal's data rate. | ||||
| RDIVider | Sets the data-rate divide ratio used to compute loop bandwidth. | ||||
| ♦ | ♦ | ♦ | ♦ | ||
| RELock | Locks clock recovery to the data rate. | ||||
| ♦ | ♦ | ♦ | ♦ | ||
| SOURce | Selects data input connector for clock recovery. | ||||
| ♦ | ♦ | ♦ | ♦ | ♦ | |
| SSClock | Selects nominal symbol rate when recoverying the clock on Spread Spectrum Clock (SSC) signals. | ||||
| ♦ | ♦ | ||||
| STYPe | Queries if continuous (as opposed to discrete) data rate settings supported? | ||||
| ♦ | ♦ | ♦ | ♦ | ||
| TDENsity? | Returns the calculated edge density of the data signal. | ||||
| ♦ | |||||
| TOData | Selects triggering on data instead of recovering the clock. | ||||
| ♦ | ♦ | ♦ | |||
The 86108A and 86108B modules provide two electrical channels for clock recovery. When sending a clock recovery command to the modules, specify slot one (1) for the subsystem, for example :CRECOVERY1:LOCKED?. Do not use :CRECOVERY3:LOCKED? as slot 3 is not a valid selection.
- Send the
:CRECovery1:CLBandwidthcommand to specify a loop bandwidth between 15 kHz to 20 MHz (86108B) or 15 kHz to 10 MHz (86108A). - Send the
:CRECovery1:CRATecommand to specify the data rate (unbanded tuning). - Send the
:CRECovery1:LOCKed?query to determine if the module is locked on the signal. - Sent the
:CRECovery1:LSELectcommand to select the Type-2 PLL loop transition frequency (peaking). - Send the
:CRECovery:PRESetscommand to load a previously saved or factory provided clock recovery settings. - Send the
:CRECovery1:RELockcommand to establish lock and to reestablish lock whenever a setup parameter changes (for example input port or trigger on data), the data rate changes, or the signal parameters change (for example, edge density). - Send the
:CRECovery{1:4}:SOURcecommand to select between multiple module channels.
You can specify loop bandwidth to be based on a fixed value or a data-rate dependent value (based on data rate and data-rate divide ratio) using the :CRECovery1:LBWMode command. With a fixed loop bandwidth selected, specify a loop bandwidth between 15 kHz to 20 MHz (86108B) or 15 kHz to 10 MHz (86108A) with the :CRECovery1:CLBandwidth command. With a data-rate dependent loop bandwidth, use the :CRECovery1:RDIVider command.
The :CRECovery1:ODRatio command can be used to specify the divide ratio that is applied to the module's front-panel Recovered Clock Output.
To calibrate the clock recovery, perform a module calibration.
Example Setup of 86108A/B Module
This sequence of commands shows one method of setting up an 86108A/B module.
:SYSTem:DEFault *OPC? :DIFF1:DMODe ON :CHAN1A:BANDwidth BANDwidth3 // BW set to 32 GHz :CHAN2A:BANDwidth BANDwidth3 *OPC? :CRECovery1:CRATe 1.03125E+10 // CDR rate set to 10 GHz :CRECovery1:CLBandwidth 5.00E+5 // CDR PLL BW to 500 kHz :CRECovery1:RELock // Lock CDR *OPC? :PTIMebase1:RSOurce INTernal :PTIMebase1:STATe ON // Turn on precision timebase :PTIMebase1:RTReference *OPC?
83496A/B Modules
Keysight 83496A/B modules provide both optical and electrical clock recovery selected by the :CRECovery{1:4}:SOURce command. These modules have continuous, unbanded tuning from 50 Mb/s to 7.10 Gb/s (14.2 Gb/s, Option 200). Specify the data rate with the :CRECovery{1:4}:CRATe command.
Because these modules do not provide automatic locking, you must issue the :CRECovery{1:4}:RELock command to establish lock and to reestablish lock whenever a setup parameter changes (for example input port or trigger on data), the data rate changes, or the signal parameters change (for example, edge density). Use the :CRECovery{1:4}:LOCKed? query to determine if the module is locked on the signal. If the module loses lock, the trigger becomes asynchronous with the data and the instrument will not display a correctly triggered waveform.
On standard 83496A/B modules select the loop bandwidth using the :CRECovery{1:4}:LBANdwidth command. On Option 300 modules, you can specify loop bandwidth to be based on a fixed value or a data-rate dependent value (based on data rate and data-rate divide ratio) using the :CRECovery{1:4}:LBWMode command. With a fixed loop bandwidth selected, specify a loop bandwidth between 30 kHz to 10 MHz with the :CRECovery{1:4}:CLBandwidth command. With a data-rate dependent loop bandwidth, use the :CRECovery{1:4}:RDIVider command.
Use the :CRECovery{1:4}:ODRatio command to specify the divide ratio that is applied to the module's front-panel Recovered Clock Output.